Loren Data's SAM Daily™

FBO DAILY ISSUE OF MARCH 03, 2005 FBO #1193
SOLICITATION NOTICE

59 -- Digital CMOS (Complementary Metal Oxide Semiconductor) IC (Integrated Circuit)

Notice Date

3/1/2005
 

Notice Type

Solicitation Notice
 

NAICS

334413 — Semiconductor and Related Device Manufacturing
 

Contracting Office

Department of Energy, Bechtel Nevada Corp (DOE Contractor), Bechtel Nevada, PO Box 98521, Las Vegas, NV, 89193
 

ZIP Code

89193
 

Solicitation Number

139571-JM-05
 

Response Due

3/21/2005
 

Archive Date

4/5/2005
 

Description

This is a source sought for the design and fabrication of a digital CMOS IC for use in digital streak imagers. Currently Bechtel Nevada Los Alamos Operations uses analog streak cameras in a VISAR (Velocity Interferometer System for Any Reflector) system. We are currently in a research and development project to build and test a prototype digital streak imager. The objective is to ?Best Value? subcontract the digital CMOS IC design and fabrication to a Subcontractor with experience in photodiode and CMOS imaging system products. The Subcontractor shall design a CMOS ROIC (readout integrated circuit) attached to a photodiode array for this new Digital Streak System. These packaged IC chips shall be delivered at the end of the final phase to Bechtel Nevada. 1.0 Target Requirements The target requirements are the minimum desired requirements for the project. (2 X 256) pixel array X 512 samples per pixel 100um x 100um pixel size Arrangement of pixels allows for a coupling of 100um diameter core optical fiber with 140um outer diameter size to each pixel Allow for adjustable gains on each of the two rows of pixels 5 ns integration time; 5 ns inter-frame rate (10 ns frame rate) 12-bit digital output, >11-bit dynamic range with one or more outputs where readout rate is sufficient to maintain dynamic range System on chip design 2.0 Deliverables Deliverables will be required at the end of each of the three phases of this project. Phase 1 is concept design, schematics, preliminary layout, and modeling. This phase will start when the contract is awarded until September 30, 2005. At the end of this phase we will have a Preliminary Design Review. The deliverable is a report sent to all parties attending the Preliminary Design Review two weeks prior to the review including: Circuit simulation outputs Preliminary IC Layouts (pixel cells, memory cells) System block diagrams including a listing of already designed blocks vs. design from scratch blocks Preliminary performance predictions Organize Preliminary Design Review by September 30, 2005 Phase 2 is the IC layout designs, layout models, and simulations. This phase will start October 1, 2005 and run for 6 months, pending funding and a satisfactory Preliminary Design Review. A Final Design Review will take place at the end of Phase 2. The deliverable is a report sent to all parties attending the Final Design Review two weeks prior to the review including: Complete IC layouts Parasitic extractions Post layout simulations with parasitics Final performance predictions including the requirements listed in section 3.1 Organize Final Design Review once Phase 2 is completed. Phase 3 is the fabrication and packaging of the ICs and full functional test to verify IC chip meets or exceeds the target requirements. The deliverables are the packaged IC chips, the corresponding data sheet, and final reports. Upon delivery we will have a receipt inspection. This phase will start after the end of Phase 2 and run for 6 months pending funding and assuming we have a satisfactory Final Design Review. An optional portion of Phase 3 is designing and building the imaging system. The deliverables include: Minimum 8 packaged IC chips tested for functionality verification The chip data/specification sheets All interested parties shall submit product brochures, capability statements or other descriptive literature, which provides sufficient detail to enable preliminary functional evaluation. Information should be faxed to the attention of Jeanette Matthews (702) 295-2088 or email the information to matthejl@nv.doe.gov. Request all information be provided no later than March 21, 2005
 

Place of Performance

Address: Bechtel Nevada, Los Alamos Operations, 182 East Gate Rd, Los Alamos, NM

Zip Code: 87544

Country: USA
 

Record

SN00760090-W 20050303/050301211732 (fbodaily.com)
 

Source

FedBizOpps.gov Link to This Notice
(may not be valid after Archive Date)

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