SPECIAL NOTICE
A -- WORKSHOP ON INTRA-CHIP COMMUNICATION
- Notice Date
- 2/3/2006
- Notice Type
- Special Notice
- NAICS
- 541710
— Research and Development in the Physical, Engineering, and Life Sciences
- Contracting Office
- Other Defense Agencies, Defense Advanced Research Projects Agency, Contracts Management Office, 3701 North Fairfax Drive, Arlington, VA, 22203-1714
- ZIP Code
- 22203-1714
- Solicitation Number
- Reference-Number-2006-7036962253
- Response Due
- 2/20/2006
- Archive Date
- 3/7/2006
- Description
- The Microsystems Technology Office (MTO) of the Defense Advanced Research Projects Agency (DARPA) is organizing a workshop to discuss the technical challenges and opportunities for photonic intra-chip communication for ultradense two-dimensional (2D) and three-dimensional (3D) chips. Increasing device density and higher operating speeds impose ever-increasing demands on communications between devices and functional units on an ultradense chip. Photonic technologies offer potential advantages for communications and this workshop will focus on a discussion of innovative ideas that could enable photonics to meet the challenging demands of intra-chip communications. We are explicitly interested in an open discussion on pros and cons of photonic and electronic intra-chip communications and the most promising technologies and approaches. While we envision the development of photonic intra-chip communications as being potentially beneficial for any ultradense chip, we focus on photonic intra-chip communications for high-performance microprocessors in order to make the discussion more concrete. We pose a set of questions to the community in attempting to address this topic: ? Are there clear and significant (quantifiable) benefits associated with using photonics for intra-chip communications? What are the opportunities? Challenges? What are the right metrics for measuring performance improvement in intra-chip communications? How would these communication benefits quantitatively translate into processor performance improvements, if implemented today or at a future technology node? What are the relevant performance requirements on photonic devices (modulators, detectors, etc.) to enable such high-performance photonic intra-chip communications? How can the stringent size, power, tunability, and other performance requirements for photonic devices be met? How can such photonic devices and infrastructure essential for intra-chip communication be integrated into traditional electronic chips in a manner compatible with modern CMOS processing? Are there novel photonic communication architectures that would be significantly superior to current electronic communication architectures? What are the most promising methods of fabrication of these chips? How can chip design technologies take advantage of photonic communications? Please note that this workshop is not a formal solicitation for proposals or proposal abstracts. The workshop is planned for March 27-28, 2006 near Arlington, VA, and will be by invitation only. If you have innovative ideas that address these or other issues germane to photonic on-chip communications and would like to attend the workshop, please send a one-page write-up to Matthew Rogers (Matthew.Rogers.ctr@darpa.mil) by February 20, 2006. Your write-up should include a brief description of the materials you would like to present as well as an overall description of your position regarding this technology area. We will inform you of our decision by February 24, 2006. A website with further information on the workshop and for registration will be provided at that time. The government will not assume liability for costs incurred for travel expenses, presentations, marketing material, etc. If there are questions related to the technical content of the workshop, please contact Jag Shah (Jag.Shah@darpa.mil 703-696-2253). Jag Shah and Dan Radack are the MTO Program Managers sponsoring this workshop.
- Record
- SN00980198-W 20060205/060203212825 (fbodaily.com)
- Source
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