SOLICITATION NOTICE
52 -- Radio Frequency System on Chip Design Toolset
- Notice Date
- 7/10/2006
- Notice Type
- Solicitation Notice
- NAICS
- 541990
— All Other Professional, Scientific, and Technical Services
- Contracting Office
- Other Defense Agencies, Office of the Secretary of Defense, Defense Microelectronics Activity, Contracting Division 4234 54th Street, Building 620, McCellan, CA, 95652-1521
- ZIP Code
- 95652-1521
- Solicitation Number
- H94003-06-R-0007
- Response Due
- 8/26/2006
- Archive Date
- 9/10/2006
- Description
- The purpose of this effort is to develop a design tool set which will combine an array of intellectual property blocks in Ultra CMOS Silicon on Sapphire technology into functional RFSoCs. The tool set will utilize IP blocks which have been proven to meet all RF requirements inherent in RF systems. The tool set will provide the capability for RFIC designers to quickly develop an RFSoC for radio systems operating at up to 3 GHz. The tool set will seamlessly integrate all RF and digital subsystem and chip-level design facets in an industry-standard software platform. It will integrate system design; analog/digital partitioning; RF integrated circuit design; device and package modeling and optimization; test generation; design validation and characterization; computer-aided-design; and a library of characterized RF circuit IP blocks. The contractor shall identify and receive written government approval from the Administrative Contracting Officer prior to committing to the use of any privately developed items, components, processes, computer software, and/or technical data which they: (i) intend to deliver with Limited Rights; (ii) intend to deliver with Government Purpose License Rights; (iii) intend to deliver with restricted rights; and (iv) have not yet determined if such rights should apply. The contractor shall perform administrative, technical, and financial management function during the course of this effort and shall maintain a status of their effort towards achieving the objectives, including all technical activities and efforts, problems/deficiencies, impacts, and recommended solutions. Contractor shall conduct technical interchange meetings as necessary in the performance of this task. Technical interchange meetings with the contractor shall be scheduled when there is need for technical interchange between the government and the contractor. The content of the meeting can include the discussion of any information that has impact upon the task activities, including documentation contents or format. The purpose of this effort is to develop a computer-based design tool set which can be used to combine an array of intellectual property blocks in Ultra CMOS Silicon on Sapphire technology into functional RFSoCs. The ?design tool set? terminology used throughout this statement comprises 3 entities. (1) EDA Tools ? Industrial standard RFIC and mixed-signal design software supplied by Cadence. (2) Process Design Kit ? RFIC/Mixed-Signal design kit with built-in IP simulation and layout capability developed by the contractor. This PDK will be used in conjunction with the aforementioned Cadence tools for the RFIC development and (3) IP Blocks ? All necessary views to complete the design, including schematic, layout, simulation test bench, measurements versus models, package rules, and usage guidelines. Contractor shall develop an integrated design tool set which can be used to combine IP blocks into functional RFSoCs. Contractor shall develop the design tool set to include a library of contractor-characterized RF circuit IP blocks based on proven components in CMOS on sapphire that have applicability to radiation hardened military, space, or commercial RF systems. The design tool set shall provide data to an RF designer which enables rapid selection of initial design blocks and guidance on modification options for application to specific system requirements. Contractor shall develop a custom process design kit based on the Cadence design tool suite to lower the cost of RFSoC system design through use of characterized RF IP blocks. The contractor shall characterize the RF IP blocks when necessary. Contractor shall fabricate test structures based upon the tool set output. The contractor shall measure test structure performance. The contractor shall demonstrate effectiveness of the design tool set through a comparison of measured vs. modeled test structure performance. The contractor shall compare development time, parts count, assembly steps, and size of equivalent RF functions using the tool set versus non-RFSoC approaches. Contractor shall demonstrate transferability of the tool set by selecting an RF systems company and then installing and validating the tool set in its Cadence design environment. Alternatively, tool set transferability can be demonstrated at DMEA at a time agreed to by the contractor and DMEA. Contractor shall deliver the Tool Set to the Government on either Compact Disk or on Digital Video Disk This requirement can be accomplished at the same time as the Tool Set Transferability requirement if both are accomplished at DMEA. Contractor shall summarize all work accomplished, including significant technical accomplishments, problems encountered, solutions implemented, recommendations for improvement, and a comparison of planned schedules and costs with final performance. Data requirements are applicable to most phases of performance on this contract. See Note 22.
- Place of Performance
- Address: Defense Microelectronics Activity, 4234 54th Street, McClellan, CA 95652
- Zip Code: 95652
- Country: UNITED STATES
- Zip Code: 95652
- Record
- SN01086017-W 20060712/060710221346 (fbodaily.com)
- Source
-
FedBizOpps Link to This Notice
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