SPECIAL NOTICE
A -- Proposers' Day Announcement - Circuit Analysis Tools (CAT) Program
- Notice Date
- 7/1/2009
- Notice Type
- Special Notice
- NAICS
- 541712
— Research and Development in the Physical, Engineering, and Life Sciences (except Biotechnology)
- Contracting Office
- Office of the Director of National Intelligence, Intelligence Advanced Research Projects Activity, Washington, District of Columbia, 20511, United States
- ZIP Code
- 20511
- Solicitation Number
- dni-iarpa-baa-09-09
- Point of Contact
- William E. Vanderlinde,
- E-Mail Address
-
dni-iarpa-baa-09-09@ugov.gov
(dni-iarpa-baa-09-09@ugov.gov)
- Small Business Set-Aside
- N/A
- Description
- Circuit Analysis Tools Proposers' Day SYNOPSIS The Intelligence Advanced Research Projects Activity (IARPA) will host a Proposers' Day Conference for the Circuit Analysis Tools (CAT) Program on July 24, 2009 in anticipation of the release of a new solicitation in support of the program. The Conference will be held from 8:30am to 4:00pm in the Washington, DC metropolitan area. The purpose of the conference will be to provide information on the CAT Program, to address questions from potential proposers and to provide a forum for potential proposers to present their capabilities for teaming opportunities. This announcement serves as a pre-solicitation notice and is issued solely for information and planning purposes. The Proposers' Day Conference does not constitute a formal solicitation for proposals or proposal abstracts. Conference attendance is voluntary and is not required to propose to future solicitations (if any) associated with this program. PROGRAM DESCRIPTION AND GOALS The semiconductor electronics industry continues to scale in accordance with Moore's law, and is currently developing the processing and design infrastructure to realize the 22nm technology node and beyond. However, analysis tools, instrumentation, and methods have not kept pace with the need for improved analytical capability. Numerous challenges arise in the wake of such rapid progress. Rapidly decreasing critical dimensions lead to die-level visual and non-visual defects at the nano- and atomic-scale, which will demand increased resolution in tools that are still able to analyze areas as large as 10 microns. Increasing numbers of transistors require more levels of metal interconnect (approaching 12 by the 22 nm node), which further complicates fault isolation, circuit edit and analysis techniques. In many cases, the only access to the transistors is through the back-side of the silicon, which requires extensive sample preparation and the need to work with creative approaches from both front- and back-side to test individual transistors. In some cases it will be necessary to advance or develop entirely new techniques to address nano-scale analysis at a comparatively large working distance and through intervening materials. Advanced packaging solutions to address the problem of increasing power dissipation and integration will require new back-side and through-packaging fault isolation approaches. The test time and hence the cost will become prohibitive with the increasing density and complexity of the logic chips. The CAT program is specifically interested in tools that are necessary for analysis at future technology nodes, specifically, the 22nm node and beyond. This also includes analysis tools capable of working with the packaging of these advanced technology nodes including but not limited to stacked die. Furthermore, the CAT program is interested in tools and techniques that can address fault isolation, circuit edit, logic analysis and image analysis for which there is currently no solution. This is analogous to the "red" boxes for technology issues in the International Technology Roadmap for Semiconductors (ITRS) annual reports (http://www.public.itrs.net/). The goal of the program is to address challenges for which existing techniques have no clear evolutionary path to the 22nm node. The CAT program is looking for significant improvements in tool technology, including revolutionary tools and techniques that provide the ability to make electrical and physical measurements on future ICs. Collaborative efforts/teaming among potential performers will be strongly encouraged. It is expected that teams will be formed to enhance the likelihood of program success due to the depth of expertise and infrastructure required to succeed against aggressive technical goals. IARPA anticipates that based on the compelling strength of the self-selected teams, universities and companies from around the world will participate in advancing the state of the art in this area. Researchers will be able to publish their findings in publicly-available, peer reviewed academic journals. REGISTRATION INFORMATION Attendees must register no later than 5:00pm EST July 17, 2009 at http://conference.brtrc.com/cat_pd/registration. Directions to the conference facility and other materials are available on the website. Due to space limitations, attendance will be limited to the first 150 registrants and to no more than 2 representatives per organization. All attendees will be required to present a government issued photo identification to enter the conference. ADDITIONAL INFORMATION The late morning and afternoon will include Presentation & Poster sessions to provide an opportunity for attendees to present organization capabilities and to explore teaming arrangements. Details on the presentation and poster formats, and the procedure for submitting a request to present, will be provided after approval to register for the Conference has been granted. Opportunities to present will be limited by time and will therefore be limited to the first 15 registered respondents with IARPA approved presentations, and the first 30 registered respondents with IARPA approved posters. These presentations are not intended to solicit feedback from the Government, and Government personnel will not be present during these sessions. This Proposers' Day is intended for participants who are eligible to compete on the anticipated BAA. Other Government Agencies, Federally Funded Research and Development Centers (FFRDCs), and University Affiliated Research Centers (UARCs) will not be eligible to submit proposals to the anticipated BAA or participate as team members under proposals submitted by eligible entities. While such entities are not prohibited from attending the Proposers Day, due to space limitations, preference will be given first to those organizations that are eligible to compete. IARPA will not provide reimbursement for costs incurred to participate in this conference. Electronic devices with the ability to record are prohibited at this event. Questions concerning conference & registration can be sent to IARPAevents@brtrc.com. Questions regarding the program can be sent to dni-iarpa-baa-09-09@ugov.gov.
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