SPECIAL NOTICE
A -- ADVANCED MISSION PROCESSOR FOR SPACE (AMPS)
- Notice Date
- 3/11/2010
- Notice Type
- Special Notice
- NAICS
- 541712
— Research and Development in the Physical, Engineering, and Life Sciences (except Biotechnology)
- Contracting Office
- Department of the Air Force, Air Force Materiel Command, AFRL, Space Vehicles Directorate, Kirtland AFB, 2251 Maxwell Ave, Kirtland AFB, New Mexico, 87117
- ZIP Code
- 87117
- Solicitation Number
- RFI-AFRL030310RVSE
- Archive Date
- 5/15/2010
- Point of Contact
- Ken Hunt, Phone: 505-846-4959
- E-Mail Address
-
ken.hunt@kirtland.af.mil
(ken.hunt@kirtland.af.mil)
- Small Business Set-Aside
- N/A
- Description
- THIS IS A REQUEST FOR INFORMATION (RFI) NOT A REQUEST FOR PROPOSAL OR SOLICITATION RFI REFERENCE NUMBER - AFRL030310RVSE RFI for Advanced Mission Processor for Space (AMPS) The Air Force Research Laboratory, Space Vehicles Directorate is issuing this request for information (RFI) to solicit information on developing and demonstrating an Advanced Mission Processor for Space (AMPS). AMPS is intended to significantly improve onboard data and signal processing for next-generation space systems. It is expected that the development will leverage commercial processing architectures / fabrics (e.g., multicore), intellectual property (IP), and/or integrated circuit (IC) fabrication processes. This notice is not to be construed as any type of request for proposal. The Government does not intend to award a contract on the basis of this request or to otherwise pay for the information solicited. Any responses submitted will not be received or interpreted as a proposal. Background Space computing falls into two broad categories: processing to support the spacecraft bus (satellite control) and processing supporting the mission payload. Satellite control requires modest processing but high reliability, and is not the subject of this RFI. Mission payload processing may have to deal with modest to high data requirements, processor speed, and memory access, while some applications may allow occasional errors, depending on type of data, frequency of collection, and criticality of the mission. Commercial electronics have gone to billions of instructions/sec (GIPS)-level performance and multicore for both consumer and specialized applications. Space processing state-of-the-art, however, is typified by "sub-GIPS" single-core architectures, augmented by application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and other support processing circuits. In space processing architectures, on-chip memory (Level 1 cache) is limited, and availability of usable Level 2 cache memory is limited. As a compromise, space systems with limited missions and orbits have used commercial processors, compensating for faultsby approaches involving temporal and spatial redundancy (e.g., triplicating and voting the processing) to assure valid operation in the harsh space environment. Requirements and Enabling Capabilities Addressed by Advanced Space Processing Onboard processing for satellite applications is constrained by reliability in the space radiation environment (radiation hardness) and by power (including heat removal). To meet the needs of next-generation space systems, advanced processors will require substantial gains in performance and energy efficiency (e.g., >10 GIPS performance and >1 GIPS/W). As a minimum, radiation hardness will need to include resilience against total ionizing dose and tolerance to single event effects (with some missions including dose rate specifications). Sophisticated, high-speed input/output must be supported, and mission lifetimes in excess of 10 years. The Air Force Research Laboratory (AFRL) has an on-going and historic interest in electronics subsystem technology maturation projects that are applicable to AMPS concepts. AFRL is considering a diversity of development and demonstration projects involving AMPS concepts, ranging from new technologies (e.g., three-dimensional circuitry, asynchronous/multi-value computation) and processes, to those involving the adaptation of contemporary components and architectures for effective use in the space environment. We are concerned with not just effective near-term approaches, but those that also extend to support a broad planning and development horizon (i.e., > 2030). To provide a framework for responses to this RFI and to encourage responses from component and subsystem technology suppliers as well as system integrators, eight key aspects of space computing have been identified. Space Computing Aspects 1. Component architecture 2. Core types, feature sets, and scalability/extensibility 3. Embedded memory configuration and distribution 4. Interconnect strategy within chip, between chips, and intra-system 5. Software strategy 6. Radiation hardness and reliability assurance approach and anticipated goals 7. Business strategy 8. Anticipated scope of space applications The above list does not presume a Government priority of these aspects. The following expanded descriptions of the space computing aspects provide additional details but are not meant to be all-inclusive. 1. Component architecture: Describe the overall use of computing elements (one or more), how they access the memory, and how they communicate internally. Is the architecture suitable for narrowly-focussed applications, or is it broadly applicable to the widest spectrum of computation problems of interest? Homogeneous versus heterogeneous processing elements, shared versus global memory, static versus dynamic network, network topology, are some of the trades that should be considered and described. A key element of the architecture description should be origin, that is, open versus proprietary, commercial versus special-purpose or unique; and state of maturity (demonstrated versus under development). 2. Core types, feature sets, and scalability/extensibility: The computing element or elements can be described as processing cores with characteristics such as word-length, pipeline organization, floating point versus fixed point, estimated instructions or operations per second, processing concurrency, thread-intensive (general purpose) versus stream-intensive (special focused on processing chores with highly regular structure), memory bandwidth, and extensibility. A key element of the core(s) description should be origin, that is, open versus proprietary, commercial versus special-purpose or unique; and state of maturity (demonstrated versus under development). 3. Embedded memory type, size, and distribution: The on-chip memory strategy and notions of caching hierarchy are critical to optimizing performance of the core(s). If DRAM is proposed, its architecture (e.g., DDR, QDR) should be included. 4. Interconnect strategy within chip, between chips, and intra-system: Interconnect strategy should include discussion of internal as well as external interconnect fabrics. If stacked or 3-D technology is proposed, interconnect discussion will be the major focus area. What types of communications protocols are expected/supported, how scalable are these fabrics? 5. Software strategy: Software strategy includes maturity and availability of support for legacy code as well as existence of assemblers, compilers, debuggers, and support for partitioning and network management for multiprocessor solutions. 6. Radiation hardness approach and reliability assurance and anticipated goals: Radiation hardness is often traded for performance and density.We are interested in understanding this trade space in particular, which features and "knobs" might be available to tune to achieve objectives of performance vs. reliability. The Government is not setting a firm set of hardness goals for this RFI, but expects responses to discuss: baseline hardening strategy (levels and approach), level of understanding of architecture, core, or memory vulnerabilities, and penalties (e.g., size, performance) for added hardness. 7. Business strategy: This aspect includes a description of the anticipated technology node (described by the technology and minimum feature size, e.g., 90nm bulk CMOS, 32nm fully depleted SOI), estimate of physical die size, potential costs, cost-sharing arrangements, risks, technology development requirements and the associated timelines for developing the concept. Information about block developments, spiral developments or initial system development with limited capabilities is also requested in this aspect. Potential teaming strategies should also be described, particularly for companies with limited space electronics business experience. 8. Anticipated scope of space applications: It is requested that responses include information regarding the applicability of the processing approach to potential space mission applications. Information about both narrowly focused and broadly applicable processing approaches is encouraged. The purpose of this Request for Information (RFI) is to gather information to assess the feasibility of funding research to identify potential AMPS concepts, including the range of algorithm types that they would be best suited for and to gauge industry interest and capability. THIS IS A REQUEST FOR INFORMATION ONLY. This RFI is issued solely for information and planning purposes. It does not constitute a solicitation (Request for Proposal or Request for Quotations) or a promise to issue a solicitation in the future. This RFI does not obligate the government in any manner for any future acquisitions. Responders are advised the government will not pay for any costs incurred as a result of response to this RFI. All costs associated with responding to this RFI will be solely at the responding party's expense. This is not a notice of intent to contract. The government does not intend to award a contract on the basis of this RFI or otherwise pay for information solicited. Data Submission Requirements Qualified participants are invited to submit and or demonstrate their interests and capability in writing. Company responses are to be submitted UNCLASSIFIED and should include a name and telephone number of a point of contact having the authority and knowledge to clarify responses with government representatives. Responses shall include a one-page cover letter identifying their company's name, address, telephone number, point of contact, and their business status (e.g., small business, large business, non-profit) and a narrative summary of no more than twelve (12) pages. Companies are not limited to a single response. Submissions are due NLT 14 May 2010 at 3:00 PM MDT. Responses may be made by mailing your response on a CD-R disk or two (2) hard copies to: Air Force Research Laboratory/RVSE Attn: Advanced Mission Processor for Space (AMPS) Mr. Ken Hunt 3550 Aberdeen Ave SE Kirtland AFB, NM 87117-5776 The Government prefers a non-proprietary submission; however, should the response contain PROPRIETARY information or trade secrets, it shall be clearly marked on each page, as applicable. The Government shall not be liable for or suffer any consequential damages for any proprietary information not properly identified. Proprietary information will be safeguarded in accordance with the applicable Government regulations. For questions regarding this RFI, the Technical point of contact is Mr. Ken Hunt, AFRL/RVSE, (505) 846-4959. Responses to questions from interested parties will be promptly answered and provided equally to all interested parties unless some release of proprietary information is involved or the answer addresses a question peculiar to a Company or that Company's possible solution. Currently one-on-one sessions with respondents are not contemplated. If one-on-one sessions with interested parties are conducted, they will be offered to all to clarify understanding of the submittal and the capability ramifications. This information is requested to support government planning activities. An Industry Day is not planned. The Government reserves the right to contact respondents for clarification or additional information. THE INFORMATION RECEIVED WILL NOT OBLIGATE THE GOVERNMENT IN ANY MANNER NOR WILL THE GOVERNMENT REIMBURSE CONTRACTORS FOR ANY COSTS ASSOCIATED WITH SUBMITTALOF THE REQUESTED INFORMATION. THIS REQUEST DOES NOT CONSTITUTE AN INVITATION FOR BID OR A REQUEST FOR PROPOSAL.
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