SOURCES SOUGHT
59 -- Northrop Grumman (NG) Airborne Sensor / Pod Technical Information
- Notice Date
- 5/31/2018
- Notice Type
- Sources Sought
- NAICS
- 339999
— All Other Miscellaneous Manufacturing
- Contracting Office
- Department of the Army, Army Contracting Command, ACC - APG (W911QY) Natick (SPS), 10 General Green Avenue, Building 1, Natick, Massachusetts, 01760-5011, United States
- ZIP Code
- 01760-5011
- Solicitation Number
- W911QY-18-C-JCAS-A-Airborne
- Archive Date
- 6/30/2018
- Point of Contact
- Nathan C Jordan, Phone: 5082336169
- E-Mail Address
-
nathan.c.jordan.civ@mail.mil
(nathan.c.jordan.civ@mail.mil)
- Small Business Set-Aside
- N/A
- Description
- (U) REQUEST FOR INFORMATION (U) Northrop Grumman (NG) Airborne Sensor / Pod Technical Information 24 April 2018 1. (U//FOUO) BACKGROUND. The Government currently procures, updates, fields, operates, sustains, and maintains multiple airborne Intelligence, Surveillance, and Reconnaissance (ISR) pods and systems built or developed by Northrop Grumman (NG). Northrop Grumman is the original equipment manufacturer (OEM) for a variety of airborne Electronic Warfare (EW) systems including, but not limited to, TONTO and SANTA FE. NG is recognized as the technical expert when it comes to developing, repairing, and training for their airborne sensors. The intent behind this effort is to facilitate in the development of a Joint Common Airborne Sensor Architecture (JCAS-A) utilizing technology and best practices from across industry to expand operational capability, reduce logistics costs, increase interoperability, and shorten development timelines. 1.1 (U) This is a Request for Information (RFI) for planning purposes only, as defined in Federal Acquisition Regulation (FAR) subpart 15.201(e). This is NOT a solicitation for proposals, proposal abstracts, or quotations. Responses to this notice are not offers and cannot be accepted by the Government to form a binding contract. The Government will NOT pay for information and materials received in response to this RFI and is no way obligated by the information received. 2. (U) SCOPE. This section describes scope of the RFI and information required by the Government. The intent of this RFI is to determine: 2.1 (U) Technical information outlined in Section 3 that is owned by the Government that was funded in the procurement and development of all NG airborne sensors / pods. 2.2 (U) Technical information outlined in Section 3 considered by NG as Internal Research and Development (IRaD). 2.3 (U) Any potential costs associated for Government procurement of IRaD information, by line item. 3. (U) REQUESTED INFORMATION. The following paragraphs outline information system description and development environment of each airborne ISR sensor and pod. The list below is not exhaustive, and the Government requests NG provide any additional technical information not included below that may be applicable to the development of the JCAS-A. 3.1 (U) SYSTEM DESCRIPTION INFORMATION. 3.1.1. (U) System block diagram (e.g. chassis level), to include: Identification of all modules (e.g. 3U VPX modules, mezzanine cards, black-box units, storage); Identification of how modules interconnect (over backplanes, front panel cables, etc.); Indicate physical location (e.g. inside/outside chassis, backplane slot position); Indicate function(s) performed by each module (transceiver, RF / Digital switch, signal processing, data processing, data storage, etc.); Include manufacturer, part number, modifications (for COTS and Modified COTS). 3.1.2 (U) System functional description (i.e. chassis-level), to include: Functional modes (high level functional overview - performing acquisition, tracking, SAR, LOB, etc.); Calibration modes; and test modes / built-in test / power-on-test, and any other modes not listed. 3.1.3 (U) System ICD (i.e. chassis level), to include: Identify Backplane profile (OpenVPX centralized, distributed, etc.); Identify connectors (SFP+, SMA, etc.); Identify pinouts; Identify transport standards and bandwidth (Ethernet, PCIe 4x Gen 2.0, etc.); Identify control and data formats (i.e. message structure, VITA 49, complex I/Q, bytes order, and any other formats not listed.) 3.1.4 (U) System datasheet (i.e. chassis-level), to include: Identification of chassis power for each voltage line (i.e. Voltage and max current) over the backplane; Tuning frequencies range and step size; RF input/output dynamic range (dBm). 3.1.5 (U) System user manual (i.e. chassis-level), to include: Instructions for setup procedures; login information; and how to run / execute existing system functions. 3.1.6 (U) Module block diagrams (i.e. card-level, and XMC, FMC, etc.), to include: Major components (e.g. CPU, FPGA, mezzanine connectors) and internal interconnects; and function(s) performed by each component. 3.1.7 (U) Modules functional description (i.e. card-level, and XMC, and FMC, etc.), to include: High level description of each module function (digital processing, RF processing, switch, etc.); Interdependencies between module(s) to express system function (e.g. Time Frequency Reference card, Transceiver card, etc.). 3.1.8 (U) Module ICDs (i.e. card-level, and XMC, and FMC, etc.), to include: Module VPX profiles; Module connectors and pinouts; Transport protocol at the module (PCIe, etc.); and data formats (VITA 49, custom, etc.). 3.2 (U) DEVELOPMENT ENVIRONMENT FOR EACH MODULE. 3.2.1 (U) Reference design(s), to include: Source code (for FPGA and SW) for reference design; Software test bench and Field Programmable Gate Array (FPGA) simulation environment for reference design; Work instruction to build, configure, and run reference design; Build log / report for end-user for SW and FPGA; and reference applications that exercise basic APIs to demonstrate useful system functions. Useful functions include, but are not limited to: RF Frontend control (Tx, Rx frequency, attenuation, etc.); Memory Access (memory controller read / write to SRAM, etc.); Push and pull data between module and processing devices (FPGA-to-FPGA, FPGA-to-CPU, etc.); Register read / write access; User I/O (ethernet, serial, etc.). 3.2.2 (U) Software Development Kit (SDK) (entire environment to modify, build, and test all reference SW applications), to include: Tool chain versions; Operating System (OS), Board Support Package (BSP), and library, and binaries dependencies; Source code, libraries and binaries to build, deploy and execute application on processor; Description of work instruction to build, deploy, and execute; Description of software APIs (e.g. reset/control/status, test, firmware loading, DMA, RF front end configuration); Delivery of software development as Virtual Machine with pre-installed cross complier, build environment, and any other information for a module to quickly ramp up new developer; Procedure to install, load and run the SW on the system; Specify and provide any emulation environments for SW applications. 3.2.3 (U) FPGA Development Kit (FDK) (entire environment to modify, simulate, build, and test all reference FPGA designs), to include: Specify simulation, synthesis, place-and-route tool versions; Provide module and top-level simulation testbenches, bus-functional models, test vectors, and documentation; Provide any design project settings, scripts, Makefiles, etc.; Platform source code, libraries and binaries to build, deploy and execute application on FPGA; Specify work instruction for FPGA build process; Specify work instruction for deploying FPGA image; Specify work instruction for user register read and write access on each FPGA. 3.2.4 (U) Specify all third party intellectual property (IP) or software licenses required to build and run the system, such as: GH Integrity OS; Northwest Logic DMA; Xillinx JESD204B; Trellisware FEC decoder. 4. (U//FOUO) SUBMISSION INSTRUCTIONS: Responses shall be submitted and received via Email in accordance with dates listed. Documents shall be no more than 10 pages total, electronic in Microsoft Word, Excel, Power Point, and/or Adobe Portable Document Format (PDF) and provided as attachments to the Email. No telephonic responses to this RFI will be considered. Request identification of documents, drawings, software, third party applications by configuration management artifact reference identifier (drawing number, software version release, third party application model and revision number, etc...). 5. (U//FOUO) ADDITIONAL INFORMATION. All information received in response to this RFI that is marked proprietary will be handled accordingly. Responses to the RFI will not be returned. Responses to this RFI are not offers and cannot be accepted by the Government to form a binding contract. Responders are solely responsible for all expenses associated with responding to this RFI. Please be advised that Government support contractors will have access to any and all information submitted under this requirement.
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