SOURCES SOUGHT
A -- Partnership Opportunity Document for NASA's Goddard Space Flight Center (GSFC) Advanced Research and Development Support
- Notice Date
- 6/4/2018
- Notice Type
- Sources Sought
- NAICS
- 336419
— Other Guided Missile and Space Vehicle Parts and Auxiliary Equipment Manufacturing
- Contracting Office
- NASA/Goddard Space Flight Center, Code 210.S, Greenbelt, Maryland, 20771, United States
- ZIP Code
- 20771
- Solicitation Number
- NASA-GSFC-POD-Advanced-RESEARCH-AND-Development-Support
- Point of Contact
- James MacKinnon, Phone: (301) 286-4785
- E-Mail Address
-
james.mackinnon@nasa.gov
(james.mackinnon@nasa.gov)
- Small Business Set-Aside
- N/A
- Description
- Partnership Opportunity Document for NASA's Goddard Space Flight Center (GSFC) Advanced Research and Development Support dated June 4, 2018 TABLE OF CONTENTS SECTION PAGE 1.0 Introduction/Scope 3 1.1 Cost 3 1.2 Desired Mission Services 3 1.3 Proposal Support 4 2.0 Project Overview 4 3.0 Technical Requirements 4 3.1 General 4 4.0 POD Response Instructions, Format, and Selection Criteria 5 4.1 Instructions 5 4.2 Format 5 5.0 Evaluation Factors and Criteria 6 6.0 Point of Contact: 6 7.0 Final Due Date of POD Response 6 8.0 Acronyms 7   1.0 INTRODUCTION/SCOPE This proposal opportunity is in response to the NASA Space Technology Mission Directorate (STMD), Early Career Initiative which was released on April 4th, 2018. NASA's Goddard Space Flight Center (GSFC) is developing a mission concept called "A Neural Network Accelerator for Space Hardware" to be proposed for this call. The partnership opportunity is being issued to select a teaming partner to provide necessary expertise in the areas of high-performance, high-reliability Field Programmable Gate Array (FPGA) development, and a thorough understanding of artificial intelligence including, but not limited to, convolutional and recurrent neural networks. Additionally, extensive knowledge of compiler internals and how to build/extend them, will be required to perform this work. Upon selection of this proposal, the partner will support operations for a total of 2 years. The STMD Early Career Initiative (ECI) enables early career NASA technologists to lead hands on development projects to deliver transformative technologies while teaming with world-class external innovators and exploring new approaches from other research and development organizations. The following schedule should be used as a basis for responses to this opportunity: Partnership Opportunity Document released June 4, 2018 Responses due June 14, 2018 Partner Selection announced June 30, 2018 Project Proposal Due to NASA HQ June 30, 2018 Project Selection Notification August 15, 2018 Project Start Date October 1, 2018 Project Midterm Continuation Review October 1, 2019 Project Completion September 30, 2020 1.1 COST If selected, the project can receive up to $1.25M in total annual funding (procurement and labor), for up to two years. This project has a total cost cap of $500,000 for all partners over the two year period. Partner will not be involved in proposal submission. Partner funding will begin at project start date should the candidate mission concept be competitively selected. 1.2 DESIRED MISSION SERVICES GSFC is interested in formally establishing a partner to provide the following services for this Early Career Initiative: Research and Development. This will include development and delivery of Field Programmable Gate Arrays (FPGA) based neural network hardware accelerators, and compilers to support the developed hardware accelerators. The partner will be expected to work closely with GSFC during the development process. All interested parties are required to respond to this POD in accordance with Section 5 below. 1.3 PROPOSAL SUPPORT No proposal support will be required from selected partner. 2.0 PROJECT OVERVIEW Imagine a new generation of space exploration with the ability to use the computational approaches behind such advanced artificially intelligent systems as Amazon's Alexa, Apple's Siri and a variety of self-driving vehicles. Working with our academic partners, our team will create a system that will allow NASA to leverage the massive investment in Artificial Intelligence (AI) research and development that has already been made in the private sector. Industry has spearheaded the use of Artificial Intelligence as an enabling technology with proven results, able to perform machine activities to an accuracy and level of detail that many NASA engineers hunger for. However, the current era of terrestrial AI has bypassed the needs of AI in space. Autonomous vehicles on earth rely heavily on powerful, but power hungry, microprocessors and Graphics Processing Units (GPU) unsuited for space. Similarly, the AI used in advanced speech recognition is not performed locally but remotely, in the cloud. Optimizing systems to perform these tasks in space requires a different paradigm. Our early career team's proposed solution is not dependent on the next generation space processing capability that has been the assumed development path for space AI. Instead, it utilizes existing radiation tolerant devices by leveraging recent discoveries in how to more effectively perform Machine Learning tasks. In this project we propose to design and build the artificial deep Neural Network Accelerator for Space Hardware that will work reliably in the harsh environment of space. We propose to do this by using a new, unique AI architecture that intelligently redistributes the internal AI processing model to allow us to target radiation hardened FPGA instead of high powered but space-unsuitable GPUs used in the current terrestrial state of the art. This exciting, high potential marriage of new methods with existing hardware can advance the state of the art to create new, advanced opportunities for lunar entry, descent and landing, rover navigation, and scientific discovery and exploration. 3.0 TECHNICAL REQUIREMENTS 3.1 GENERAL The partner will support GSFC in the development of a general purpose neural network accelerator FPGA core. The accelerator should be able to: • Compute feed forward neural networks of several types including: o Fully Connected (or Dense) o Recurrent o Convolutional • Handle direct memory transfers of both user data and model weights • Be programmable in a high level API such as Google's TensorFlow Included in this work is a compiler backend that will target the new accelerator core. This will serve the purpose of translating high level TensorFlow function calls to the low level microcode being run in the accelerator. A compiler is necessary to enable to usage of TensorFlow with the accelerator to enable a much simpler and more flexible NN design process and also to allow for the usage of preexisting TensorFlow NN models like GoogLeNet or Visual Geometry Group Neural Network (VGGnet). 4.0 POD RESPONSE INSTRUCTIONS, FORMAT, AND SELECTION CRITERIA 4.1 INSTRUCTIONS The respondent shall: • Provide information on proven previous FPGA designs which demonstrate knowledge and skill suited to this particular task. Previous work should be relevant to implementing neural networks on FPGAs and the difficulties that entails. For example, designs requiring high performance and highly optimized memory transfers, high clock speeds, and large amounts of arithmetic will be necessary. • Demonstrate understanding and quantified experience in the design, integration, and testing of the FPGA system proposed. The response shall describe how the proposed accelerator meets the requirements given in Section 3. • Demonstrate understanding of compilers through previous work in the development, modification and design of compilers. • Demonstrate experience in building 2D convolution hardware accelerators. • Demonstrate experience and knowledge of high level synthesis, and its usage in practical applications. • Provide publications in reputable conferences and journals detailing previous work. • Provide a preliminary budget including expected costs such as estimated FTE required, cost of labor, and required development hardware (e.g. FPGA Development Kits, Test Equipment). • Provide a brief statement of work defining participation in the ECI. 4.2 FORMAT The response to this partnership opportunity is limited to 6 pages in not less than 12-point font. Excluded from the page count are the cover letter, title pages, table of contents, and acronym list. Partners may attach additional appendices that further describe their capabilities, although GSFC is under no obligation to include the contents of such appendices in the evaluation of the offer package. The entire offer package, including any cover letter, title pages, and other supporting material, shall be formatted as a Portable Document Format (PDF) file delivered to the E-mail address below. 5.0 EVALUATION FACTORS AND CRITERIA The evaluation team will use the following factors in selection and award: 1. Technical Approach (40%). Offerors will be evaluated on their ability to meet the instrument technical requirements given in Section 3. This includes demonstrated understanding of the requirements and proposed approach to meet those requirements. 2. Cost (20%). Offerors will be evaluated on their overall cost and on the reasonableness of cost and schedule estimates. 3. Relevant Experience and Past Performance (40%). Special emphasis will be given to demonstrated experience with similar developments, particularly with regards to FPGA development, compilers, artificial intelligence, machine learning, and neural networks. 6.0 POINT OF CONTACT: Questions about this POD should be directed to James MacKinnon (Phone: 301-286-4785 Email: james.mackinnon@nasa.gov). 7.0 FINAL DUE DATE OF POD RESPONSE The response to the POD is due no later than 5 p.m. EDT on June 14, 2018. The electronic PDF document shall be sent to James MacKinnon (Email james.mackinnon@nasa.gov) It is the responsibility of potential respondents to monitor the following site: http://fbo.gov for information concerning this POD.   8.0 ACRONYMS ECI Early Career Initiative AI Artificial Intelligence NN Neural Network GSFC Goddard Space Flight Center FPGA Field Programmable Gate Array ICD Interface Control Document NLT No Later Than NPR NASA Procedural Requirements PDF Portable Document Format PI Principal Investigator POD Partnership Opportunity Document SOW Statement of Work TBD To Be Determined U.S.A United States of America
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