Loren Data's SAM Daily™

FBO DAILY - FEDBIZOPPS ISSUE OF JUNE 06, 2018 FBO #6039
SPECIAL NOTICE

66 -- Notice Of Intent to Sole Source - Silterra, Inc.- Fabrication CMOS

Notice Date

6/4/2018
 

Notice Type

Special Notice
 

NAICS

334413 — Semiconductor and Related Device Manufacturing
 

Contracting Office

Department of Commerce, National Institute of Standards and Technology (NIST), Acquisition Management Division, 100 Bureau Drive, Building 301, Room B130, Gaithersburg, Maryland, 20899-1410, United States
 

ZIP Code

20899-1410
 

Solicitation Number

NB620020-18-02561
 

Archive Date

7/3/2018
 

Point of Contact

Joni L. Laster, Phone: 3019756205, Forest Crumpler, Phone: 3019756753
 

E-Mail Address

joni.laster@nist.gov, forest.crumpler@nist.gov
(joni.laster@nist.gov, forest.crumpler@nist.gov)
 

Small Business Set-Aside

N/A
 

Description

The United States Department of Commerce (DOC), National Institute of Standards and Technology (NIST), Acquisition Management Division (AMD) intends to negotiate a firm fixed price purchase order, on a sole source basis, with Silterra, Inc. for the fabrication of up to 20 wafers with customized CMOS circuitry via a tape-out from a semiconductor foundry for the Center for Nanoscale Technology Science and Technology (CNST) Electron Physics Group. The statutory authority for this sole source acquisition is FAR 13.106-1(b) by the authority of FAR Part 13.5 Simplified Acquisition Procedures for Certain Commercial Items. The Electron Physics Group in the Center for Nanoscale Science and Technology at the National Institute of Standards and Technology (NIST) requires the purchase of customized CMOS wafers based on flexible tape-out runs for a wafer-scale 0.18um CMOS chip fabrication process. The CMOS wafers received would be used as a first step in developing a measurement and application testbed for novel electronic devices that are currently being manufactured at the Center for Nanoscale Science and Technology (CNST). Such an integrated measurement and application testbed will be used for parasitic-free novel device characterization as well as non-invasive imaging of complex circuits and systems as a part of CNST's mission to develop nanoscale measurement and characterization capabilities in support of users in the user facility. Currently measurement and characterization of nanoscale resistive switches are limited by the parasitics and noise constraints of the measurement system that prevent accurate programming and evaluation of resistive states. Moreover, observation of information flow throughout complex hybrid CMOS+resistive switch based systems would require a large amount of flexibility, such as massive amount of invasive test points for current and voltage measurement that would deteriorate the performance of such a system. Monolithically integrating the measurements with customized CMOS wafers would eliminate both issues, as devices would suffer from much lower parasitics and direct imaging of information flow through non-invasive thermo-reflectance measurements would be possible. NIST has an ongoing Cooperative Research and Development Agreement with the University of California at Santa Barbara (UCSB) to collaboratively design and fabricate resistive switching neuromorphic circuits based on wafer-scale CMOS chip tape-outs. The tape-outs required for this procurement will be used in this collaboration and the agreement commits NIST to provide some space on the wafers to the UCSB to design their own circuits. Our collaborators at the UCSB have been designing CMOS chips using Silterra's proprietary processes. Therefore, to continue using their existing circuit designs, Silterra is uniquely qualified, as NIST and UCSB require the process in the new tapes-outs to be 100% compatible with Silterra's proprietary processes and only Silterra can comply with NIST's obligations under the existing CRADA with UCSB. Delivery shall be FOB DESTINATION and shall occur not later than 120 days after design acceptance. The North American Industry Classification System (NAICS) code for this acquisition is 334413, and the size standard is 1250 employees. No solicitation package will be issued. This notice of intent is not a request for competitive quotations; however, all responsible sources interested may identify their interest and capability to respond to this requirement. The Government will consider responses received by established due date/time set forth in this notice. Inquiries will only be accepted via email to joni.laster@nist.gov. No telephone requests will be honored. A determination by the Government not to compete the proposed acquisition based upon responses to this notice is solely within the discretion of the Government. Information received will normally be considered solely for determining whether to conduct a competitive procurement in the future.
 

Web Link

FBO.gov Permalink
(https://www.fbo.gov/spg/DOC/NIST/AcAsD/NB620020-18-02561/listing.html)
 

Place of Performance

Address: 100 Bureau Drive, Gaithersburg, Maryland, 20899, United States

Zip Code: 20899
 

Record

SN04942815-W 20180606/180604230818-0867ccabe0900852ca03d0bb60d57e95 (fbodaily.com)
 

Source

FedBizOpps Link to This Notice
(may not be valid after Archive Date)

---

| FSG Index  |  This Issue's Index  |  Today's FBO Daily Index Page |