SPECIAL NOTICE
59 -- Request for Information: Partnerships for Coupling Innovation and Manufacturing Through Critical On-shore Prototyping
- Notice Date
- 2/24/2022 11:17:49 AM
- Notice Type
- Special Notice
- NAICS
- 334416
— Capacitor, Resistor, Coil, Transformer, and Other Inductor Manufacturing
- Contracting Office
- NSWC CRANE CRANE IN 47522-5001 USA
- ZIP Code
- 47522-5001
- Solicitation Number
- N0016422SNB42
- Response Due
- 4/5/2022 1:00:00 PM
- Archive Date
- 05/20/2022
- Point of Contact
- Matthew Kay, Phone: 8128610865
- E-Mail Address
-
matthew.j.kay.civ@us.navy.mil
(matthew.j.kay.civ@us.navy.mil)
- Description
- N0016422SNB42 � Request for Information: Partnerships for Coupling Innovation and Manufacturing Through Critical On-shore Prototyping � PSC 5961 � NAICS 334416 Issue Date: 24 February 2022 - Closing Date: 05 April 2022 Synopsis The Office of the Under Secretary of Defense for Research and Engineering (OUSD(R&E)) is seeking information from the domestic microelectronics (ME) community to help inform DoD�s objectives, assumptions, and initiatives pursuant to the Fiscal Year (FY) 2021 National Defense Authorization Act (NDAA) (Pub. L. 116-283), including the CHIPS (Creating Helpful Incentives to Produce Semiconductors) for America Act, and pending legislation on potential funding of these efforts through the United States Innovation and Competition Act (USICA) and passage of the America Creating Opportunities for Manufacturing, Pre-Eminence in Technology, and Economic Strength (America COMPETES) Act of 2022.� The FY 2021 NDAA legislation significantly emphasizes solutions that promote the domestic on-shoring of capabilities to address economic and technology security concerns. Under Sec. 9903(b), DoD is directed to establish a National Network for Microelectronics Research and Development (NNMRD) to enable the laboratory-to-fabrication transition of microelectronics innovations in the United States and to expand the global leadership in microelectronics of the United States. Specifically, DoD is requesting information to inform objectives, assumptions, and approaches to addressing a component of the NNMRD, the �Microelectronics Commons,� through a public-private partnership consisting of regional innovation hubs distributed across the U.S. to foster a pipeline of innovative ideas and talent residing in university labs and small business R&D teams.� Note that this response does not target the National Network for Next-generation Microelectronics Manufacture, a part of ERI 2.0 (see below), which was previously addressed in RFI DARPA-SN-21-06. For this RFI, we are seeking input from a broad range of institutions, including academia, startups, small businesses, technology incubators, government labs, federally funded research and development centers (FFRDCs), the defense industrial base (DIB), and domestic semiconductor manufacturers.� Please note that this RFI covers Section 9903(b) of the CHIPS Act.� DoD has issued a separate RFI (Reference Number: N0016422SNB36, PSC: 5961, NAICS: 334413) to specifically collect industry input for the strategy development in response to FY21 NDAA Section 9903(a) to help inform DoD proposed commercial provisions for inclusion into potential public-private semiconductor industry agreements. �Furthermore, the Department of Commerce issued a separate RFI to solicit information to inform the design and implementation of the incentives program authorized by Section 9902, and the R&D programs including the National Semiconductor Technology Center authorized under Section 9906. �To avoid duplication, responses may reference input provided in the separate DoD RFI with any additional information applicable to the proposed Section 9903(b) ME Commons construct described herein. Background U.S. technological dominance in ME materials, processes, devices, and architectural designs can only be sustained through the development of a robust domestic innovation ecosystem that fosters the rapid development and transition of novel concepts into commercially viable manufacturing processes. The U.S. innovation ecosystem has long been the driver of our nation�s technology leadership throughout the world.� U.S. R&D kick-started the enormous semiconductor industry and continues to lead the world in developing the next generation of disruptive technologies including: new materials, devices, circuits, architectures, and design tools.� In recent years, the efficient domestic adoption of U.S. chip innovation has been threatened as emerging hardware technologies have become increasingly reliant on offshore sources for State of the Art (SOTA) manufacturing, prototyping, and investment. There are several significant hurdles that hardware startups face, including limited or expensive access to necessary facilities and design infrastructure, high costs of design intellectual property, limited expertise with hardware engineering, and high costs of prototyping.� As a result, the number of U.S. hardware startups has dropped significantly and foreign investment in U.S.-based technology startups has enabled offshore fabrication and maturation of emerging technologies.� Related Microelectronics Initiatives To address these challenges, the DoD has pursued a multifaceted approach to strengthen the domestic ME ecosystem.� The OUSD(R&E) Trusted and Assured ME (T&AM) program leverages commercial technology to enable DoD programs� access to advanced ME required for modern and vastly more capable defense systems.� Through these engagements, T&AM is accelerating development and transition of SOTA technologies through prototype demonstrators in which partnerships with commercial ME vendors are enabling the design and manufacture of integrated circuits (ICs) and multi-chip packages (MCPs) optimized for DoD.� T&AM�s efforts are developing a measurably secure methodology compatible with commercial processes across the entire ME supply chain including design, fabrication, packaging, and test. � USG R&D initiatives have continued to play a critical role in supporting U.S. technology leadership.� DARPA�s Electronics Resurgence Initiative (ERI), created in 2017 as a five-year investment, continues to increase commercial industry engagement in defense-related research and provides a foundation to ensure future U.S. leadership in microelectronics.� DARPA�s ERI 2.0 follow-on effort will focus on leap-ahead technologies to keep the U.S. at the forefront of ME technology in the areas of next-generation three-dimensional microsystem design, fabrication, packaging, assembly, and testing, and the prototyping of these microsystem technologies.� Additionally, the National Science Foundation maintains a range of complementary R&D programs across the full hardware stack associated with microelectronics research in academic institutions. Through the Department of Commerce (DOC), the National Semiconductor Technology Center (NSTC) and the advanced packaging, metrology, and manufacturing USA programs authorized under Sec 9906(c), (d), (e), and (f) of the FY 2021 NDAA, are expected to strengthen the research and innovation ecosystem for microelectronics and semiconductor R&D in the U.S.� These programs will invest in the infrastructure necessary to better integrate advances in research into semiconductor manufacturing.� This includes providing facilities to support near-term R&D and advanced prototyping, which the U.S. ecosystem currently lacks.� These activities are intended to demonstrate the potential large-scale manufacturing feasibility of ME innovations that support broad application areas and promote economic viability of U.S. Problem To supplement substantial U.S. investments in disruptive R&D, DoD must organize and facilitate a national network of research entities by reducing innovation barriers and enhance existing infrastructure.� These research entities may be adjacent or within academic or other facilities that support local or regional ME ecosystems. Many restrictions exist for introducing new materials and processes into tightly controlled high-volume fabrication processes where high yield to offset large facility operation costs.� New models, science, and technology must be leveraged to create a different manufacturing paradigm based on proven process tools in agile fabrication facilities (fabs). These enhanced manufacturing capabilities could allow cost-effective ways to capture and incentivize domestic R&D and provide a low-volume production environment for a high mix of technologies as they are incubated and nurtured for DoD and commercial market applications. Solution Sought To address these needs, a public private partnership is envisioned, consisting of regional innovation hubs distributed across the U.S. to foster a pipeline of innovative ideas and talent residing in university labs and small business R&D teams.� The partnership will provide resources for and access to specialized lab equipment, technical expertise, and connections to existing or upgraded low-volume prototyping facilities.� These low-volume fabrication and packaging facilities will help mature promising technologies and demonstrate the manufacturing and economic benefits of these innovations for dual-use application for defense and commercial sectors. The USD(R&E) Microelectronics Commons will focus on critical, on-shore prototyping to transition innovation from universities, start-ups, and small companies to manufacturing.� Key features are: Creates and connects �Lab-to-Fab� testing/prototyping hubs to form a network focused on maturing emerging microelectronics technologies Provides broad access to these prototyping hubs, potentially by augmenting academic facilities and enabling access to facilities within local semiconductor companies or FFRDCs.� Facilitates ME education and training of students at local colleges and universities, and provide a potential pipeline to bolster local semiconductor economies and contribute more broadly to the growth of a domestic semiconductor workforce. Envisioned Organizational Structure ME Commons Management Organization (MCMO): An independent Commons Management Organization will be established to provide efficient coordination and administration of the regional innovation hubs. The MCMO will be tasked with selecting and operating the network, in alignment with the OUSD(R&E) feedback and vision to ensure DoD access to and benefit from resulting technologies.� The MCMO will conduct the competition to select the hubs from existing entities and operate them in collaboration with local management. The management organization would provide oversight responsibility to facilitate the administrative, legal, and business functions of the hubs, and will report directly to the government-designated program manager. The management organization can also coordinate and manage regional hub access to shared resources such as licenses for electronic design automation (EDA) tools and cutting-edge fabrication facilities. This eliminates the need for each regional hub to establish relationships with foundries and EDA tool vendors and avoids duplication of efforts across the network. Innovation Hubs: These consortia of regional facilities will be organized in collaboration with the MCMO to address DoD needs and requirements.� Existing academic facilities will be augmented to enhance intrinsic specializations in emerging areas of ME. The Commons will include multiple hubs to support opportunities and innovation within the spectrum of regional markets across the U.S. �Ideal hub candidates will leverage and enhance existing prototyping capabilities at academic or small business facilities that include myriad instruments, material deposition chambers, lithography, test and measurement tools etc. �Selection of a hub will also be based on the opportunities for workforce development.� This may include MCMO sponsorship of technology demonstration efforts and the potential to augment the existing professional staff of highly-skilled and trained engineers and scientists to complement concurrent investments in new prototyping capabilities. �Academic institutions and small businesses within a hub can both act as a sources of innovation as well as a host for sponsored efforts. �While these hubs would prioritize DoD funded activities, these capabilities would be available to researchers supported by other agencies based on demand. SOTA Commercial Fabs: Creating a path for successful Lab-to-Fab technology transition involves significant industry buy-in from SOTA fabs.� The ME Commons will establish early and sustained engagement with industry and academic stakeholders to build consensus on technology roadmaps to guide maturation and delivery of innovation into a given commercial fabricator�s pilot line and production plans.� Scope Through MCMO administration, the ME Commons will promote a synergistic effort between academia, commercial industry, and DoD to identify and select dual-use technology advances that are ready for maturation.� The main focus will be on identifying viable emerging technologies and new device and circuit concepts that are both sufficiently practical and also sufficiently high impact.� Typically, these would be technologies proven in a lab (technology readiness level (TRL) 3-4) which would be matured through the Commons to facilitate transition into advanced prototyping capabilities such as those enabled by the NSTC.� RFI Questions Microelectronics Commons Management What are some best practices for establishing an independent MCMO to ensure flexibility and responsiveness to regional market needs and alignment with government and defense needs? What issues specific to the ME Commons concept should DoD consider when developing an approach to public-private partnerships? How can the government leverage existing DoD initiatives, for example DMEA�s Center of Excellence for establishing public-private-partnerships, the Defense Innovation Unit (DIU) and DARPA�s ERI program, to support the ME Commons concept? What would encourage and facilitate non-traditional defense contractor and commercial entity participation? What considerations are needed to ensure the balance between the security of USG information and intellectual property while promoting competitiveness? What factors should DoD consider in IP licensing agreements? What are cost-sharing models/mechanisms that can be leveraged to ensure long-term viability and sustainment of the program? Technology Innovation and Transition Considerations What are the major barriers and infrastructure limitations faced by your organization in maturing and prototyping innovation within the domestic ecosystem? What are some best practices to coordinate and manage regional hub access for shared resources such as licenses for EDA tools and cutting-edge fabrication facilities, in order to eliminate the need for innovators to establish relationships with foundries and EDA tool vendors and avoid duplication of efforts? How can partnerships facilitate introduction of new materials and processes into tightly controlled high-volume fabrication processes that rely on maintaining high yield to accommodate large facility operation costs?� How can new models, science, and technology be leveraged to create a different manufacturing paradigm based on proven process tools in agile fabs? How can partnerships and new manufacturing capabilities provide cost-effective ways to capture and incentivize domestic R&D in a low-volume production environment for various semiconductor technologies as they are matured and transitioned for DoD and commercial market applications? Identify a potential opportunity within a specific U.S. region having a strong presence in advanced microelectronics and outline the business case including roles and engagement of key stakeholders including: University Research labs, University Affiliated Research Centers Technology Startups Defense Industrial Base Federally Funded Research and Development Centers and National Labs Commercial industry drivers Business incubators SOTA Commercial Fabs Government, and public ME-focused laboratory resources What are the most critical existing or near-term domestic microelectronic technology areas needs/gaps supporting DoD systems? The ME Commons concept will connect to and complement other efforts described in the �Related Microelectronics Initiatives� above. �What considerations should be given to ensure strong integration between these efforts? Should there be overlap in the technology readiness levels served by each program? What criteria should be considered in identifying viable emerging technologies and new device and circuit concepts that are both sufficiently practical and also sufficiently high impact to warrant technology maturation and sustained interest by critical DIB and Commercial Industry partners? Typically, these will range from emerging technologies proven in a lab (technology readiness level (TRL) 3-4) which would be matured through the Commons to facilitate transition into advanced prototyping capabilities such as those enabled by the NSTC.� What existing technologies meet these criteria and would be ideally suited to technology maturation in the near term (1-2 years)? What specific resources are needed for specialized lab equipment, technical expertise, and connections to existing or upgraded high-mix low-volume prototyping facilities to help mature these promising technologies?� How can a regional partnership facilitate education and training of students at colleges and universities, and provide a perennial pipeline for an educated and trained workforce that bolsters US semiconductor leadership? RFI Submission and Contact Information In the RFI response, please provide your name(s), contact information, the company/entity and industry sector that the response represents. Responses can be provided in word format as a white paper not to exceed ten pages.� Responses will not be made public.� Please provide answers to the RFI Questions contained herein, and submit RFI response by April 5, 2022.� Please reference Announcement Number: N0016422SNB42 with any response to this RFI. If you have any questions about this RFI, please reach out to Mr. Matthew Kay, the Navy representative for the Defense Microelectronics Cross-Functional Team (DM CFT). at matthew.j.kay.civ@us.navy.mil or (812) 661-0865. Eligibility OUSD(R&E) invites participation for this RFI to all institutions, including academia, startups, small businesses, technology incubators, government labs, FFRDCs, the DIB, and domestic semiconductor manufacturers that are part of or provide services to any part of the US microelectronics innovation ecosystem supporting defense procurements, commercial entities, and non-traditional defense contractors as defined in section 2302 of title 10 of the United States Code (10 U.S.C. � 2302 (9)).� Interested parties must be properly registered in the System for Award Management (SAM) and may obtain information on SAM registration and annual confirmation requirements by calling 1-866-606-8220 or via the internet at https://www.sam.gov.� Disclaimer This RFI is the initiation of market research under FAR Part 10. This announcement does not constitute an Invitation for Bids (IFB), a Request for Quote (RFQ), or a Request for Proposal (RFP) and it should not be construed as a commitment of any kind by the Government to issue a formal solicitation or ultimately award a contract. Participation in this RFI is strictly voluntary. Responses to this notice cannot be accepted as offers. The United States Government is in no way liable to pay for or reimburse any companies or entities that respond to this announcement. Any costs incurred by interested companies in response to this announcement will NOT be reimbursed. Nothing in this announcement constitutes an obligation on the part of the United States Government.
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