Commander, Code 240000D (Bldg 91044), Naval Air Warfare Center Weapons Division, 1 Administration Circle, China Lake CA 93555-6001

70 -- SCHEMATIC DESIGN/SIMULATION AND PRINTED CIRCUIT BOARD LAYOUT TO OLS SOL N68936-95-Q-F961 DUE 090195 POC Sheryl Allen, Contracting Officer, 619/939-9659. The Naval Air Warfare Center Weapons Division, China Lake, California, intends to procure a Schematic Design/Simulation and Printed Circuit Board Layout tools, supported on Microsoft Windows platforms. The Printed Circuit Design Software must include: (1) A Printed Circuit Board with over 3,000 connections and parts database. The Printed Circuit Board layout software should provide autoplacement, rip-up/retry autorouter, and automated assembly outputs. (2) A parts library equivalent to that provided by PADS-Perform, which is a general industry basis for comparison. (3) A bi-directional interface between the PCB design databases and the standard Data exchange File format. (4) Tools for automatic clustering and placement of components with on-line Design Rule Check (DRC) of component interference. Automatic and interactive modes for cluster creation and cluster placement. (5) An autorouting tool with multiple algorithms, interactive autorouting with on-line DRC and batch autorouting modes. (6) Tools for verifying the electro dynamic properties of the Printed Circuit Board design database, checking for parallelism, tandem, capacitance, resistance, impedance and connection lengths. The Schematic Design Software must include: (1) An integrated design capture environment with Very High-speed-integrated-circuit Hardware Description Language (VHDL), Advanced Binary Expression Language (ABEL), and schematics, including an integrated symbol editor, and a wide array of symbol sets and parts libraries. (2) Automatic schematic generation to create readable schematics for analysis and documentation. (3) A bi-directional interface between schematic entry and PCB design tools. (4) Digital simulation for rapid functional and gate-level verification and full pre and post layout timing simulation, including a graphical wave form definition and analysis tool. (5) A high-performance, multi-level VHDL simulation for a complete, top-down, behavior-to-gates simulation capability. (6) Multi-level synthesis to automatically create optimized designs from VHDL descriptions using a wide variety of technologies and libraries. (7) Design and analysis of Programmable Logic Devices (PLDs) and Complex Programmable Logic Devices (CPLD), including automatic partitioning, timing model and fusemap generation. (8) A bi-directional interface between schematic entry and Electric Design Interchange Format (EDIF) compatible Electronic Design Automation (EDA) tools from other vendors. Expected delivery schedule is 30 days ARO. All responsible sources may submit an offer which will be considered. Solicitation will be issued on or about Sept 1, 1995 and will close 15 days thereafter. (0227)

Loren Data Corp. http://www.ld.com (SYN# 0277 19950816\70-0002.SOL)