NCCOSC RDTE Division Code 02214B 53570 Silvergate Avenue Bldg A33 San Diego CA 92152-5113

A -- MODIFICATION: SILICON ON INSULATOR (SOI) MATERIAL & PROCESS EVALUATION SOL N66001-95-X-8004 DUE 123196 POC Contract Specialist, Ed Brown, (619)553-5725. Contracting Officer, Mark Lopez. Bid Clerk, JC Norris, (619)553-4331. The Naval Command, Control and Ocean Surveillance Center (NCCOSC) RDTE Division (NRaD) and the Microelectronics Technology Office (MTO) of ARPA are seeking sources to measure and provide data on Silicon On Insulator (SOI) wafers in exchange for wafers provided by MTO. This data/wafer exchange is intended to support the Low Power Electronics (LPE) Program. The government is presently in the process of defining and evaluating SOE wafers being developed under this program. Using SEMATECH as a specifying and clearing house, the development and evaluation of SOI wafers is a key to the success of the LPE program. Because these wafers are new in the industry, the government wishes to make some of them available to organizations (commercial and university) which can evaluate them with respect to their processes or needs, and provide the resulting test data back to the government. The potential sources must be currently unfunded within the LPE program: that is they are not associated with existing program contracts. Under the exchange program; there will be no money exchanged as part of the data/wafer exchange, direct or indirect. In order to request wafers, the potential sources must identify the following parameters: a. Type and diameter of SOI wafers (4'', 5'', 6'', 8'', SIMOX, Bonded) (Full specifications and process details for wafer size reduction will be provided to the requestor.) b. Number of wafers requested (by type and diameter) and time frame of delivery. c. General set of wafer specifications required--Si film thickness, Uniformity and Resistivity--BOX thickness and Uniformity--Wafer bow and warp--Edge contour--Wafer flatness and orientation--Any other special characteristics desired. (Note: - SEMATECH will characterize and screen all the key material specs under development and improvement including but not limited to: ++Surface cleanliness (defects, metals, particles)++BOX electrical quality (leakage, breakdown, charge)++Si electrical quality (lifetim);++Si film structural quality (disclocation density, HF defects, surface microroughness, OSF, voids etc).) In addition, the SOI wafers will be provided with data sheets on all major material specifications and quality metrics measured non-destructively. The destructive data will be provided on 1 or 2 samples from the same batches lots of the materials provided. Data will include all key items in the spec sheet. The potential sources must submit a test plan describing the evaluations that will be done on the SOI wafers, the purpose of the evaluations, the resources for performing the evaluations, and a schedule of the work to be done. This detail test plan must list all key devices and test chip structures to be measured and the device/yield data that will be provided as feedback. The following results will be required as a minimum: ++NMOS & PMOS statistical device data for VDD at 1,2,3,4 V including threshold voltage, off state leakage, subthreshold slopes, Idsat mean values and uniformity++Gate oxide quality (breakdown reliability histograms)++Ring oscillator or other circuit performance (speed, power) data. All the results should be provided as a documentation to SEMATECH and the government. SEMATECH can provide characterization assistance of processed wafers if requested. Test plans may be submitted any time prior to 31 DEC 1996. (Evaluations of the test plans will be performed by the government and SEMATECH.) Test plans should provide in detail a program plan, size of required wafer, a detailed test plan, test equipment, test result format, and data expected to be provided to the government. Any test equipment proposed to be used must have been demostrated to be operational within the parameters, precision and accuracy planned by the experiment. None of the equipment shall be Government Furnished Equipment (GFE) or procured by the government. In the case where a potential source wishes to do testing with equipment on purchase, or planned, any agreement to provide wafers will be subject to the demonstrated operation of the test equipment, prior to implementation. Acceptance of all or part of the test plan and wafer exchange may be made at any time throughout the period and will take the form of memorandums of agreements. The technical point of ontact is Dr. C. H. Hanson, NCCOSC RDTE Division, Code 8505, 53560 Hull St. Rm. 2070, San Diego, CA 92152-5000, e-mail chanson@nosc.mil, commercial (619)553-5242, fax (619)553-1161. All test plans and technical inquires should be addressed to the above individual. The above announcement is intended to support a Government wafer exchange for data project. There are no government funds available for this project. (0276)

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