Department of the Navy, NAWCAD Contracts Competency Division, MS32, 22541 Millstone Road, Patuxent River, MD 20670-5304

70 -- SIGNAL PROCESSING HARDWARE AND SOFTWARE SOL N00421-96-R-1085 DUE 050996 POC Karen Y. Gunter, Contract Specialist, (301) 342-1825 Ext. 209 Rebecca J. Wathen, Contracting Officer, (301)342-1825 Ext. 133. This is a notice of intent to negotiate with Catalina Research Inc., 1321 Aeroplaza Drive, Colorado Springs, CO 80916-2247 on an other than full and open competitive basis for the purchase of 1 ea CRCV1M40-64-C6 Digital Signal Processor Board with Filter Coefficient Update Option and ANSI C assembler and 1 ea 12SM-1226-RV6/6J123-P750-CRI 6 slot 6U / 6 slot 9U VME chassis with 750 Watt power supply. This hardware and software is needed to support the required testing of U.S.Navy and U.S. Air Force airborne radar systems. The Government intends to negotiate on a sole source basis with Catalina Research Inc. because Catalina Research Inc. offers the only multi-processor, single board digital signal processor with VMEbus compatible, 9U form factor, D32, A24 and A16 data transfer and address modes, interrupt capability that can perform a 1024 point, 24 bit, block floating point FFT/Multiply/FFT every 25.6 microseconds or less, and provide a High Speed Coefficient Update Port for adaptive frequency domain convolution processing at a sustained rate of 60 Million Complex Samples Per Second. The end result of the unique highly pipelined FFT processor configuration is that the required sample generation throughput and output to Digital to Analog Conversion for radar target return generation for this very specific application can only be achieved with this architecture. The vendor for this specification shall provide a Digital Signal Processor module with the following capabilities: 1) The board shall occupy one VMEbus compatible, 9U form factor slot and shall support D32,A24 and A16 data transfer and address modes and interrupt capability. 2) the board shall continuously perform a 1024 point, 24-bit, block floating point FFT/Multiply/FFT every 25.6 microseconds or less (continuous 40Mhz complex data processing) 3) The board shall provide a High Speed Coefficient Update Port for frequency domain convolution processing. 4) The board shall provide one 50 Million Complex Sample Per Second data port for input and one 50MCSPS data port for output on the front panel. 5) The board shall support correlation, sectioned convolution and filtering algorithms. Responses to this notice of intent should be addressed to Karen Gunter at the above address. Submitted responses should include a capability statement and other pertinent qualifications. See Numbered Note(s): 22. (0088)

Loren Data Corp. http://www.ld.com (SYN# 0276 19960329\70-0001.SOL)