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A -- PART 1 OF 3. ADVANCED DIGITAL RECEIVER TECHNOLOGY SOL N66001-96-X-6903 DUE 082296 POC Contracting Officer, Ed Brown, (619)553-5725. BROAD AGENCY ANNOUNCEMENT (BAA) for Digital Receivers (DR). Proposals are being sought for a Digital Receiver, a program supported by DARPA/ETO. Three primary focus areas of interested are (1) Digital Receiver, (2) Mixed Signal High Precision MultiChip Module, and (3) Technology Extensions in Digital Receiver Components. The goal of this program will be substantial reductions in size and power and improvement in performance of the components as part of military electronic systems. Full proposals are being sought for Focus Areas 1 and 2, and white papers for Focus Area 3. PROGRAM OBJECTIVES AND DESCRIPTION: NRaD, in conjunction with the Defense Advanced Research Projects Agency (DARPA), is soliciting innovative research in the areas of all-digital receivers for radar, electronic warfare, and/or communications applications. This program is an extension of the DARPA HBT analog to digital converter program and Air Force Wright Laboratory programs in support of the receiver area and is expected to address advanced novel work over these programs. The Digital Receiver Program goal is to develop two types of receivers. One is a radar receiver with at least 80 dB spurious-free dynamic range (SPDR) and a signal bandwidth of at least 1 MHz. The other is an Electronic Warfare/Electronic Support Measure receiver with similar dynamic range over a multi-octave bandwidth. (The bidder shall be specific as to the type of receiver being proposed. If both, separate proposals are required: not a single proposal with options.) The two architectures are intended to support a tunable pass-band at center frequencies between 20 MHz and 18 GHz. Based upon this performance regime, DARPA anticipates that III-V or SiGe based room temperature HBT devices will be the technology of choice. However, other technologies will be considered if they can support the goals of this program. The advantages of replacing the analog portions of radar and EW systems with all-digital or mostly-digital subsystems have been discussed for at least a decade in the military radar and EW communities. The crucial missing technologies are recognized to include: a)monolithic A/D converters with sampling rates and analog bandwidths which can support digital conversion of signals closer to the antenna, coupled with superior signal to noise ratio and distortion (SINAD) and SFDR performance; b) very high speed demultiplexers to slow the digital data stream rates down to speed compatible with signal processing components; and c) high linearity, high sample rate D/A converters which not only form a portion of the A/D converters, but also could form the basis of direct digital synthesizers capable of generating very pure sine wave of varying frequencies to serve as the local oscillators in these radar and EW systems. Within the past two years, DARPA-sponsored programs to develop advanced Gallium Arsenide and Indium Phosphide integrated circuit technologies have begun to yield monolithic devices with these desired capabilities. Monolithic A/D and D/A converters with multi-GHz sample rates and good linearity, and demultiplexers with extremely high toggle and bit rates, have been demonstrated. Sufficient progress has been made in these integrated circuit technologies to persuade DARPA that a larger effort to exploit these emerging devices is warranted. The program will be composed of three Focus Areas. These areas are intended to correct the perceived limitations of the existing technology base to enable all-digital receivers for military systems. Bidders may submit multiple proposals. Each proposal may address only one focus area. In Focus Area 1, separate proposals are required for each receiver type if the bidder addresses both. It is anticipated that there will be multiple awards, each with an expected duration of 2-3 years at a funding level of less than $5M. Such awards will depend upon evaluations described below and availability of funds. The Government reserves the right to select for award, all, some, or none of the proposals received in response to this announcement. The Government may also only select specific tasks within a proposal for award. FOCUS AREA ONE: DIGITAL RECEIVER: FA-1 TECHNICAL: A notional, generic, all-digital receiver is envisioned to be fully contained on a large multichip module (MCM) or small printed wiring board (PWB), and to contain several miniaturized, interconnected subsections, all of which are candidates for initial development or improvement. The large MCM is assumed to contain the following notional submodules, each mounted on a ''daughter'' MCM: a) a tunable RF front end (eigher digital or analog) containing a noise shaping/anti-aliasing filter and low noise amplifier (LNA); b) an A/D converter and demultiplexer module; c) a backend digital signal processor (using COTS devices if available); and d) a power conditioner and e) a direct digital synthesizer for the tunable or frequency agile implementations. Bidders to this Focus Area are expected to provide aproaches to ALL SIX of the following Items: 1-Architectures; 2-MCMs; 3-Power Conditioning; 4-Design; 5-Integration; 6-Demonstration. In Item 1, the bidders shall describe their concepts for system-level architectures, including: a) refinements of DARPA's notional architecture, or definitions of their own alternate top level architectures, including the partitioning described above or their own alternate partitionings, and to document and explain the strengths of the proposed architectures; b) improvements in each of the subelements of the high level architecture in order to optimize system operating parameters such as effective number of bits (ENOB), spurious free dynamic range (SFDR), and signal to noise ratio and distortion (SINAD); c) novel ideas for analog noise shaping; d) improved approaches to the arcievement of tunability of the front end analog electronic both in center frequency and passband, e.g., through novel designs for analog mixers and low noise amplifiers (LNAs); e) novel approaches to the implementation of direct digital synthesizers; and f) a set of interface definitions for the system I/O and for the inter- and intra- module interfaces, with particular attention given to the electrical signal integrity within each interface between individual submodules, and between the large MCM and the external environment. In Item 2, in support of the architectures proposed, bidders shall provide an assessment of capabilities of the current MCM technologies, including present shortcomings and technical approaches of overcoming these weaknesses. This assessment will include issues of high precision MCM fabrication, signal integrity in mixed signal systems, and high frequency performance of MCMs. Bidders shall also provide an implementation plan for using MCM supliers in support of this program. Test coupon designs will be provided by the government to be fabricated by the selected MCM substrate fabricator, at the government's expense. The bidders may propose a teaming arrangement with Federally Funded Research and Development Centers for the development of the MCMs. The bidders shall provide a strategy for affordable DoD access to scaleable quantities of MCM technologies which result from this effort. In Item 3, Power Conditioning, bidders shall provide a strategy to provide on-module power conditioning, routing and power supplies. This strategy shall include dc power minimization, should have consideration for efficient dc-dc conversion, and effective decoupling and bypass capacitance. Innovative ideas for extending module-level power supply and/or conditioning are encouraged. In Item 4, Design, bidders shall conduct simulation, design, and fabrication of the individual components in accordance with the architecture proposed. There are no plans in this program to extend existing design tools or semiconductor technology. In Item 5, Integration, bidders shall describe their approaches to the coupling of chips to one another on a subsystem MCM, and coupling of subsystems MCMs to one another on a common substrate. Issues such as assembly, test and evaluation of the components in accordance with the system design, and data analysis shall be described. In Item 6, Demonstration, bidders shall provide a plan for a proposed demonstration. This step is intended to validate the architecture and designs proposed and implemented, with emphasis on system performance. (0180)

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