Rome Laboratory/PKPX, 26 Electronic Parkway, Rome NY 13441-4514

A -- SPECIAL NOTICE: ROME LABORATORY'S FY 97 SBIR TOPICS SOL SBIR TOPIC 10 POC Joetta A. Bernhard, Contracting Officer, A/C 315-330-2308; Margot Ashcroft, SBIR Program Manager, 315-330-1793. PART 3 OF 6. ROME LABORATORY'S FY 97 SBIR TOPIC. ROME LABORATORY IS PLEASED TO MAKE AVAILABLE THE FOLLOWING SMALL BUSINESS INNOVATIVE RESEARCH (SBIR) PROGRAM TOPICS, AS FOLLOWS: SBIR TOPIC (10) TITLE: Prognostic Assessment Technique/Tool for Electronic Equipment and Systems. TECHNICAL POINT OF CONTACT: Dr. Christopher E. Reuter, RL/ER-G, 315-330-7642. NARRATIVE: Because microelectronic semiconductor devices degrade as they age (transistor diffused or doped regions degenerate, metal/semiconductor contacts break down, metal traces degrade from electromigration, etc.) there is potential to measure system level radiated signals with external (non-contact) probing for the purpose of assessing the health of electronic equipment. The device level degradation causes reduced device and system performance. Furthermore, (as the equipment ages) this degradation may modify the ambient radiation inherent to all electronic equipment and can potentially be measured by external non-contact probing of various signals. Thus an innovative technique designed to measure and characterize life-cycle status of electronic equipment and predict necessity for replacement of system components is desired. It is envisioned that the technique/tools developed would have the capability to predict/estimate time-to-failure system under test and provide advance information on the life-cycle disposition of an electronic system. Additionally the technique should have the ability to localize degraded devices within the system. OBJECTIVE: To develop prognostic techniques and hardware for assessing health of electronic equipment/systems. DESCRIPTION: PHASE I: This consists of identifying appropriate measurable signals that are indicative of the health of electronic equipment and testing the feasibility of using these signals as a diagnostic/prognostic indicator for equipment under test. This may include simulations and empirical testing of hardware. POTENTIAL COMMERCIAL MARKET: There would be a large commercial potential from this effort. The ability to assess the health of electronic equipment could potentially dramatically impact both military and commercial practices regarding electronic equipment and maintenance. SBIR TOPIC (11) TITLE: New Diagnostic Tool for Evaluation of Material Surfaces. TECHNICAL POINT OF CONTACT: Lois D. Walsh, RL/ER-G, 315-330-2983. OBJECTIVE: Develop marketable technique for routine measurement and comparison of material surfaces during integrated circuit manufacture. DESCRIPTION: The problem is that the reliability of microelectronic devices is dependent on the consistent quality of material surfaces and interfaces. There is no one routine measurement to provide a simple complete surface description. The technical challenge is to develop a new diagnostic tool for evaluation of material surfaces to determine consistency of current manufactured lots with previous known ''good'' lots. Surface structure is known to change with deposition and substrate parameters. Presently there is no standard method to determine the quality of the surface or to compare one surface with another surface. Grain size, surface roughness, and grain orientation are parameters to be considered, but they need to be monitored and analyzed in such a way as to promote easy comparisons. One technique might be to determine the fractal dimension of the surfaces using a kinetic model with Smoluchowski equations and Jullien's solution. - Phase I Expectations: Develop robust, consistent technique for routine surface quality measurement of nanometer structures. DUAL USE COMMERCIAL POTENTIAL: A readily available technique for surface quality measurements is imperative to producing high quality reliable microelectronic devices for both commercial and military applications. Such a technique would allow in-process monitoring of microelectronic materials for surface and interface quality before addition of more value to the product. The tool would also assist small companies with older deposition equipment to produce a high quality, more reliable product. Resultant reliable devices would be available for commercial (medical, transportation and communications) and military (transportation, communications, and weapons) applications at more competitive prices. SBIR TOPIC (12) TITLE: Design Tools for Minimizing Electronic Failure. TECHNICAL POINT OF CONTACT: Martin J. Walter, RL/ER-G315-330-4102. OBJECTIVE: Develop a computer-aided design tool minimizing the failure of VLSI microcircuits and integrate them. DESCRIPTION: The failure of electronic components and systems has adverse effects on the readiness, effectiveness, availability, and affordability of military systems. It increases maintenance costs, and aggravates the quantity of spares required during deployment. Managing the failure of electronic systems and components involves building electronic systems and components that are not susceptible to end-of-life failure mechanisms, and that can perform the required functions when some of the components or some part of a component has failed. In order to build reliability into electronic components and systems, design techniques and tools must be developed which guide design processes such as synthesis and technology mapping based on reliability and fault tolerance. Reliability analysis and simulation during logic design assist in making circuits reliable. The management of failure includes constraining circuit susceptibility to failure mechanisms like electromigration through design processes such as synthesis and technology mapping, analyzing physical layouts of VLSI designs to make the design more robust, and exploiting fault tolerant design techniques to increase the reliability of the overall circuit when some portion of it has failed. The models, algorithms and techniques will be integrated into a commercializable CAD tool that can be interfaced with commercial design frameworks, and employ widely accepted design modeling languages such as VHDL.- Phase I: Define and detail the proposed algorithms that need to be developed and implemented. Create a preliminary design of the proposed methods and tools including the interfaces to commercial design frameworks. POTENTIAL COMMERCIAL MARKET: The ability to manage circuit failure during the design of the circuit, reduces the time required to develop advanced microcircuits while maintaining high confidence in the availability of electronic systems. This technology is important both for the use of these circuits in military applications and in the commercial sector. The tools developed under this topic will have a significant effect on military electronic systems because the failure of the electronics can severely damage mission success rates, increase system support costs, and the number of spares needed. The tools will reduce development time which is the driving force for commercial electronics, and defines the profitability of electronic companies. Electronic systems will benefit by reducing the number of spare parts needed when they are deployed, by reducing the amount of time needed for system repair, and by increasing the availability of the system for operational use. Tools developed for this area will reduce the overall cost and time associated with developing reliable advanced microelectronic circuits. End-of-life failure mechanisms, that pervade the circuit population, must be eliminated as early as possible during circuit development. The tools developed under this topic will enable circuit designers to minimize the circuit's susceptibility to these mechanisms, and minimize the effects of device failure on circuit performance. The tools will reduce life cycle support costs for both military and commercial electronics including automotive, communications and aerospace applications SBIR TOPIC (13) TITLE: Ultra-High Speed Bit Error Rate Tester. TECHNICAL POINT OF CONTACT: Charles W. Tsacoyeanes, RL/ER-H, 617-377-4599. OBJECTIVE: To develop a 25Gbit/s bit error rate tester. DESCRIPTION: Current fiber optic links have only partially realized the enormous bandwidth available using single-mode optical fiber. The military and the telecommunications industry have had bandwidth requirements which have been increasing each year by a factor of greater than two. These demands are driven by the transmission of images and the increase in traffic on the world wide web. Current commercial systems operate at speeds up to 2.5Gbit/s with future upgrades planned for 10Gbit/s (OC-192). The Air Force and several other government agencies have immediate requirements for data transmission rates in the 10 to 40Gbit/s range and future requirements as high as 100Gbit/s. DARPA has a new program entitled ''Ultra Photonics'' whose objective is to increase the speed of current information processing systems by a factor of 10 to 100. The components needed to build fiber optic links with data transmission rates up to 40Gbit/s are available commercially but the test equipment needed to measure their performance is not. Measurement of the performance of these systems requires a high speed bit error rate tester (BERT). The highest speed BERT available commercially is 12Gbit/s and very expensive ($300K). The goal of this program is to design, develop and commercialize a reliable and affordable 25Gbit/s BERT and establish the framework necessary to develop a 40Gbit/s BERT. The commercial availability of this instrument will accelerate the development and utilization of much higher speed fiber optic links than presently available. Collaborations are encouraged.- PHASE I: Design and demonstrate the feasibility of developing a 25Gbit/s BERT. POTENTIAL COMMERCIAL MARKET: The demand for this product will be driven by the telecommunications industry which is a multi-billion dollar market. SBIR TOPIC (14) TITLE: Large Area Nitride Substrates. TECHNICAL POINT OF CONTACT: David Bliss, RL/ER-H, 617-377-4841. OBJECTIVE: Economical large area III-N epitaxial substrates. DESCRIPTION: Nitride semiconducting devices have demonstrated capabilities for solar blind detection, visible emission for heads-up displays, short wavelength sources for ultra high density data storage and short wavelength optical communications. Cost effective manufacturing of these devices for subsystem insertion depends on the availability of large area nitride substrate materials. GaN-suitable substrates must be compatible with existing semiconductor handling equipment. GaN and related materials are currently grown by epitaxial means upon surrogate substrates. Epitaxial deposition and substrate technology must be developed to demonstrate device quality material growth on economical, large area substrates. Program expectation is for demonstration of III-Nitride growth on large area substrates, with demonstration of material quality through demonstration of optoelectronic componentry. Teaming and collaborative relations, especially in Phase II, are encouraged.- PHASE I: Experimentally demonstrate growth on 75mm substrates, and feasibility of scaling substrate diameter in excess of 150mm. POTENTIAL COMMERCIAL MARKET: GaN substrates are suitable platforms for blue lasers and blue LED's. The market for blue light emitting diodes (LED's) is expected to be as large as the present market for red and green LED's, which is on the order of 10 billion parts per year. The substrate requirement to achieve this level of production is conservatively estimated to be over one million wafers per year, or approximately $100M/yr. The estimated price of $100 per wafer is expected to come down as the volume increases over time, as new applications such as blue lasers are brought into production. (0229)

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