Defense Advanced Research Projects Agency (DARPA), Contracts Management Office (CMO), 3701 N. Fairfax Dr., Arlington VA 22203-1714

A -- MULTITHREADED AND OTHER EXPERIMENTAL COMPUTER ARCHITECTURES SOL BAA97-03 DUE 020397 POC Dr. Robert F. Lucas, DARPA/ITO, Fax: (703) 522-7161. The Defense Advanced Research Projects Agency (DARPA) solicits proposals for research and technology development related to multithreaded architecture. The Semiconductor Industries Association (SIA) Roadmap for semiconductors lays out a commercial CMOS process agenda which, over the next five years, will lead to the batch fabrication of processors containing billions of transistor circuits operating at GigaHertz speeds. Equally impressive is the continuing growth in the density of memory chips, particularly DRAMs. Unfortunately, improvements in the access times and I/O bandwidth of memory parts are not growing at a commensurate rate. As a result, the relative performance of processor and memory chips is diverging and memory latency increasing. This is further compounded by complex memory hierarchies which need to be traversed between processors and main memory. Large Defense applications will be unable to fully exploit the high-speed processors anticipated in the near future because their performance is often constrained as much by the time it takes to access data as it is by processor speed. Memory latency, while growing, is not a new phenomenon. There have been a number of techniques designed to reduce its impact on system performance. These include: vector processors, multithreaded architectures, memory subsystems supporting multiple outstanding memory requests, and deep cache hierarchies with increasingly long cache lines. All of these are compromises, trading off logic, concurrency, and bandwidth for latency. Caches are the most prevalent solution to the problem of memory latency. Unfortunately, they do not perform well if an application's memory access patterns do not conform to hard-wired policies. Perhaps the best example of this is the need for sequential stride through memory, at least locally, to achieve optimal performance. As a result, caches present the application programmer with a hierarchical view of memory that complicates coding and porting of high-performance applications. Furthermore, caches are consuming an increasingly large share of processor chips, even though their size has long since exceeded the point of diminishing returns. Vector processors have been engineered to support arbitrary strides through memory, however, they require large amounts of fine-grained, SIMD parallelism as well as complicated memory subsystems, to be effective. Multithreading is another, less well understood technique for tolerating memory latency. It too requires concurrency and complicated processors. However it offers the advantage of being able to exploit MIMD concurrency as well as interweave multiple users so as to maximize system throughput even when it cannot offer peak throughput to any single application. To better understand the problem of memory latency and to increase the utility of future computing systems to High-End Defense applications, DARPA solicits research in High-End computing architectures and experimental multithreaded computing architectures. Such research should involve innovative approaches to solving the above mentioned problems and should lead to or enable revolutionary advances in the state-of-the-art. The following three focus areas support DARPA's Information Technology Office (ITO) Scalable Computing Systems and Ultrascale Computing Programs. 1) EVALUATION OF DEFENSE UTILITY OF MULTITHREADED ARCHITECTURE. Conventional wisdom predicts that a PetaFLOP system will be comprised of a million GigaFLOP processors. In order to determine whether such systems will address Defense computing problems, DARPA solicits proposals for evaluating the effects of latency tolerance mechanisms in High-End, multithreaded computing systems. In particular, analysis of the efficacy of compilers and other tools in extracting 10,000 or more threads from Defense applications such that Amdahl's Law doesn't prevent efficient use of the overall system is sought. Simulations, emulations, or ideally measurements on prototype computing systems are required.2) DESIGN OF LATENCY TOLERANT, EXPERIMENTAL HIGH-END COMPUTING ARCHITECTURES. Just as DARPA's Reduced Instruction Set Computer (RISC) projects in the 1980's redefined the CPU, DARPA now solicits research that will redefine the processor and memory architectures of future computing systems. Mechanisms like multithreading for tolerating latency and minimizing the impact of distribution and hierarchy in large memory systems are desired. Particular emphasis will be given to proposals that can scale in processor speed to exploit novel device technologies such as Rapid Single Flux Quantum, SiGe, cryogenic CMOS, or others. 3) LOW-LATENCY COMPLEX SYSTEM DESIGN. Another way to address the problem of latency in large systems is by minimizing their physical dimensions. Proposals are sought that exploit novel device technologies, three-dimensional packaging, chemical or molecular self-assembly techniques, and innovative interconnection technologies that reduce time-of-flight induced latency between processors and memories. PROGRAM SCOPE: Proposed research should investigate innovative approaches and techniques that lead to or enable revolutionary advances in the state-of-the-art. Research should result in prototype hardware and software demonstrating integrated concepts and approaches on Defense-relevant applications. Specifically excluded is research which primarily results in evolutionary improvement to the existing state of practice or focuses on a specific system or hardware solution. Integrated solution sets embodying significant technological advances are strongly encouraged over narrowly defined research endeavors. Partnering arrangements among academic, industrial, and non-profit research organizations are strongly encouraged. GENERAL INFORMATION: In order to minimize unnecessary effort in proposal preparation and review, proposers are strongly encouraged to submit brief proposal abstracts in advance of full proposals. An original and six copies of the proposal abstract must be submitted to DARPA/ITO, ATTN: BAA 97-03, 3701 North Fairfax Drive, Arlington, VA 22203-1714, on or before 4:00 PM (ET), Wednesday, December 4, 1996, to guarantee review. Upon review, DARPA will provide written feedback on the likelihood of a full proposal being selected. Proposers must submit an original and six copies of full proposals by 4:00 PM (ET), Monday, February 3, 1997, in order to be considered. Proposers must obtain a pamphlet, BAA 97-03 Proposer Information, which provides further information on the areas of interest, submission, evaluation, funding processes, proposal abstracts, and full proposal formats. This pamphlet may be obtained by fax, electronic mail, or mail request to the administrative contact address given below, as well as at URL address http://www.ito.darpa.mil/Solicitations.html. Proposals not meeting the format described in the pamphlet may not be reviewed. This Commerce Business Daily notice, in conjunction with the pamphlet BAA 97-03 Proposer Information, constitutes the total BAA. No additional information is available, nor will a formal RFP or other solicitation regarding this announcement be issued.Requests for same will be disregarded. The Government reserves the right to select for award all, some, or none of the proposals received. All responsible sources capable of satisfying the Government's needs may submit a proposal which shall be considered by DARPA. Historically Black Colleges and Universities (HBCU) and Minority Institutions (MI) are encouraged to submit proposals and join others in submitting proposals. However, no portion of this BAA will be set aside for HBCU and MI participation due to the impracticality of reserving discrete or severable areas of information security research for exclusive competition among these entities. Evaluation of proposals will be accomplished through a scientific review of each proposal using the following criteria, which are listed in descending order of relative importance: (1) overall scientific and technical merit, (2) potential contribution and relevance to DARPA mission, (3) offeror's capabilities and related experience, (4) plans and capability to accomplish technology transition, and (5) cost realism. All administrative correspondence and questions on this solicitation, including requests for information on how to submit a proposal abstract or proposal to this BAA, must be directed to one of the administrative addresses below by 4:00 PM, January 28, 1997, e-mail or fax is preferred. DARPA intends to use electronic mail and fax for some of the correspondence regarding BAA97-03. Proposals and proposal abstracts may not be submitted by fax, any so sent will be disregarded. The administrative addresses for this BAA are: Fax: 703-522-7161 Addressed to: DARPA/ITO, BAA 97-03, Electronic Mail: baa9703@darpa.mil, Electronic File Retrieval:http://www.ito.darpa.mil/Solicitations.html, Mail: DARPA/ITO, ATTN: BAA 97-03, 3701 N. Fairfax Drive, Arlington, VA 22203-1714. (0290)

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