Rome Laboratory/PK, 26 Electronic Parkway, Rome, NY 13441-4514

A -- ADVANCED TECHNOLOGY FOR SPACE-TIME ADAPTIVE PROCESSING MODELING SOL F30602-97-R-0003 POC Capt Anthony W Wann, Contract Specialist, Rome Laboratory/PKRZ, (315)330-7690; Edward Starczewski, Laboratory Program Manager, Rome Laboratory/OCSA, (315)330-7127 CORRECTION: This action was originally published in the CBD dated 11/12/96, SECTION: Procurements. Potential offerors are advised that a conventional solicitation will not be issued. This solicitation and resulting award shall be made in accordance with the Research and Development Streamlined Contracting Procedures (RDSCP) described in DFARS 235.70. The solicitation will appear in a subsequent edition of the Commerce Business Daily. Concurrent with publication of the solicitation, a supplemental package will be mailed to all respondees. Provide address information to ATTENTION: Capt Anthony W Wann, Rome Laboratory/PKRZ, 26 Electronic Pky, Rome NY 13441-4514, in order to be included on the mailing list for any supplemental packages and/or amendments to the solicitation. No telephone requests for the solicitation will be honored. All requests must reference the code A-7-1201-Z, and contain the respondent's FAX number, e-mail address, and Commerical and Government Entity (CAGE) code. All responsible sources may submit a proposal in response to the solicitation which shall be considered. The objective of this effort is to enhance the capabilities and performance of Rome Laboratory's Space Time Adaptive Processing/Algorithm Development Tool (RLSTAP/ADT). Several new capabilities will be added to the tool, including: advanced jammer models, jammer mitigation algorithms, tracking algorithms, and Synthetic Aperture Radar (SAR) modeling and processing algorithms. Performance of the RLSTAP/ADT will be enhanced in two ways: First, all legacy Fortran code will be converted to the C programming language; Second, by optimizing the single processor version of the code and parallelizing time critical subroutines for execution on the Intel Paragon parallel architecture. See Numbered Note 26. All other information publicized in the original synopsis is correct. Refer to the original synopsis for more details. (0066)

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