US Army ARDEC, AMSTA-AR-PC, Picatinny Arsenal, New Jersey 07806-5000

A -- DEVELOPMENT OF AN INTEGRATED CIRCUIT SOL DAAE30-98-R-0500 DUE 112497 POC Ennette M. Boyiatgis, Contract Specilist, 201-724-2910 WEB: US ARMY TACOM-ARDEC Procurement Network, http://procnet.pica.army.mil/procacts.htm. E-MAIL: Ennette M. Boyiatgis, eboyiat@pica.army.mil. The US Army Armament Research, Development and Engineering Center (ARDEC) is planning award of a sole source contract for the development of an integrated circuit (IC). ARDEC intends to award to the current contractor, Integrated Circuit Systems (ICS), San Jose, CA to avoid the extenuating duplication of costs.. The current contractor has existing artwork which may be modified to accomplish the government need. The following information is offered to those contractors who feel they can effectively compete for this effort. Based on block diagrams, breadboard circuits, and an existing signal processor IC, the contractor must design a new signal processor IC which will provide increased dynamic range and increased resistance to Electronic Counter Measures (ECM). The signal processor circuit is part of a radar system for a low cost artillery fuzing application. The signal processor circuit consists of two parallel channels that include low noise amplifiers, filters, and phase shifters with bandwidths up to30 KHz. The phase shifters must provide a relative phase shift of 90 degrees between the two channels over the entire 30 KHz bandwidth. In addition, the gain and frequency response of the two channels must track one another to within +/- 5%. The present signal processor uses switched capacitor circuits to realize many of these circuit functions. Therefore, continuous-time anti-aliasing filters must be provided to avoid passing undesired frequency components at or above the clock rate. The signal processor also contains summing and differencing amplifiers, a rectifier/integrator circuit and a threshold detector. In order to maximize system sensitivity, circuit noise must be minimized. The signal processor must generate four pairs of reference waveforms. Presently, these waveforms are stored in a non-volatile memory on-chip. Each reference waveform consists of 64, 4-bit words that are clocked at a rate of 3.2 MHz. The reference waveforms drive two Digital to Analog Converters (DAC's). In addition, the signal processor must generate two additional waveforms. One waveform consists of 64, 5-bit words that are stored in a non-volatile memory. The memory is clocked at a 3.2 MHz rate into a DAC. The other waveform is a pseudo-random bit stream. New circuits to be added to the signal processor IC include a wideband summing circuit and a mixer circuit. Both of these circuits require a bandwidth in excess of 160 MHz. In addition, a zero crossing detector/hard limiter is required. System power is provided by a small battery, therefore, the signal processor IC must use a technology that minimizes power consumption. Previous versions of this signal processor have been designed fabricated using an analog/digital CMOS process. The signal processor can be designed for either a 3.3 volt or a 5 volt power supply. In order to minimize production costs, it is highly desirable to minimize die size, to place all functions on-chip and to minimize the number of external components. In addition, the integrated circuit must operate over the military temperature range of -40 C to +60 C and must survive a gun launch environment with setback forces up to 30,000 g's. The production unit cost of this integrated circuit is an important aspect of its design. The government plans on procuring between 400 thousand and 1.8 million fuzes which will utilize this device. Interested contractors are to discuss unit production cost in addition to their knowledge and experience in designing, developing and fabricating this type of integrated circuit. Facsimile responses are not acceptable. Responses shall be addressed to the above contract specialist at US Army TACOM-ARDEC, AMSTA-AR-PC-E, Picatinny Arseanl, NJ o7806-5000 to be received 15 calendar days from the date of this synopsis. See numbered Note 22. This solicitation will be available for downloading from the World Wide Wed Electronic Commerce Home Page available at the following address: http://procnet.pica.army.mil. (0311)

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