Commercial Acquisition Department, Bldg 11, Naval Undersea Warfare Center Division, Newport, Code 59, Simonpietri Dr., Newport, RI 02841-1708

70 -- DIGITAL SIGNAL PROCESSING BOARD SOL N66604-98-Q-5532 DUE 092298 POC Jeannie M. Clermont, Contracting Officer at (401) 832-1460; FAX (401) 832-4820 WEB: NAVAL UNDERSEA WARFARE CENTER DIVISION, NEWPORT, http://www.npt.nuwc.navy.mil/contract/. E-MAIL: J.M.Clermont, ClermontJMCODE59@npt.nuwc.navy.mil. SYNOPSIS of 14 AUG 98 is changed based on answers being provided for 4 questions received and resultant changes to the Performance Specification as follows: QUESTION #1 Would the required 80Mbytes/sec (minimum) bi-directional digital data path to each DSP be acceptable, if operated over two (2) Link Ports to the P2 connector? ANSWER #1 Yes, this digital path solution would be acceptable. QUESTION #2 It has been reported that Themis Computer does not offer a 5CE controller, however Force Computer does. Can we assume that a driver written for the Force 5CE controller would be compliant, or should we support another Themis controller? If so, which Themis controller? ANSWER #2 In part 3.0 of the Performance Specification under Development Software and Hardware/Software Support CHANGE "Driver software compatible with Themis 5CE controller" to read "Driver software compatible with Themis SPARC 5/64 controller" QUESTION #3 It has been determined that the Interphase 4515 PMC ATM Adapter is obsolete. Since another will have to be selected anyway, is there any other PMC ATM Adapter that would be considered a first choice? ANSWER #3 In part 3.0 of the Performance Specification under REQUIREMENTS CHANGE "Interphase 4515 PMC ATM Adapter or equivalent," to read "Interphase 4575-SM-1M PMC ATM Adapter or equivalent," QUESTION #4 The VME motherboard can be reset, however, is there a requirement to reset individual processors and if so, would the inability to support that function be considered non-compliant? ANSWER #4 There is a requirement to reset the entire motherboard as well as a requirement to reset each individual processor under software control. The inability to support these functions will be considered non-compliant. Also, in part 3.2 of the Performance Specification under Input/Output Characteristics & Configuration CHANGE "The PMC Daughtercard shall be implemented on a single-width PCI Mezzanine." to read "The PMC Daughtercard shall be implemented on a single-width PCI Mezzanine card." CHANGE deliverydate from 30 September 1998 to 16 November 1998 or earlier. Posted 09/01/98 (W-SN244266). (0244)

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