Naval Research Laboratory, Code 3220, 4555 Overlook Ave. S.W., Washington, D.C. 20375-5326

70 -- SCALABLE, SHARED MEMORY, PARALLEL, MULTI THREADED ARCHITECTURE (MTA) SUPERCOMPUTER SOL N00173-00-R-DL03 POC Contact, Dian Lockamy, 202-767-3782, Contracting Officer, Jan Bays, 202-767-2974 WEB: click here, http:/heron.nrl.navy.mil/contracts/home.html. The Naval Research Laboratory has a requirement for a scalable, shared memory, parallel, Multi Threaded Architecture (MTA) supercomputer. The system will be used to explore innovations in computer technology for solving research problems of significant military relevance relating to the physical, computational, and information sciences. The system will be integrated into NRL's existing "network centric" distributed computing environment that supports the research community and will need to complement existing equipment, including an MPP system of clustered computers, mass storage devices, visualization engines, a global filesystem based on AFS, a completely Kerberized (K5) authenticated environment, high definition progressive motion imagery (HDTV), and a high-speed network supportive of multi-gigabit stream rates. The proposed architecture will allow researchers access at NRL and within the DOD High Performance Computing Modernization Program (HPCMP) through DREN to functionally prototype applicationsrapidly using both implicit and explicit specifications of parallelism. The system is expected to be at the leading edge of scalable parallel technology and to provide an upgrade path that assures its continued competitiveness at the forefront of scalable parallel computer technology for approximately three years. The architecture must be balanced in terms of computation, communication, memory, and I/O latency and access. The system must provide a "globally shared memory paradigm", provide an AFS client running natively, be able to connect efficiently to a global fast filesystem for common scratch space, provide for loop-level parallelism, and support appropriate external communications channel adapters to interconnect to NRL's distributed computing assets, authenticated AFS-based tertiary storage systems, and the DREN wide area network. In addition to the aforementioned criteria, the baseline entry requirement for the MTA system is 16 processors (approximately 1 gigaflop per processor), 64 Gbytes of flat main memory (no memory locality issues) and demonstration of near-term scalability to 256 while maintaining even access to all memory by all processors. The system will support a paradigm of compiler-directive parallelism (such as OpenMP) as well as the ability to run applications written with the Message Passing Interface (MPI) libraries. The system will support a Fortran 77 and 90 compiler as well as C and C++ compilers. The contractor shall be responsible for equipment installation and acceptance testing, provisioning of system software, and hardware and software maintenance to include optimization and reconfiguration as necessary by NRL to meet the research user community needs over the life of the contract. Anticipated baseline system delivery is NTE 90 days after the date of the contract. The estimated period of performance is three (3) years, with provisions to provide for upgrades, enhancements, onsite and maintenance options for two added optional years. Onsite personnel need to obtain secret level security clearances. The Naval Research Laboratory uses Electronic Commerce (EC) to issue RFPs and amendments to RFPs. A detailed performance specification/description will be issued with the solicitation. This solicitation and any amendments to it will be available via the Internet at the URL address shown below. Paper copies of the RFP will not be provided. Numbered Note 26 applies. Point of contact is Dian Lockamy, Code 3220.DL, Naval Research Laboratory, 4555 Overlook Avenue, SW, Washington, DC 20375-5326. NRL Reference No. is 3220-DL03. Posted 04/12/00 (W-SN444213). (0103)

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