A -- MISSION SPECIFIC PROCESSING

Notice Date

December 8, 2000

Contracting Office

Defense Advanced Research Projects Agency (DARPA), Contract Management Office (CMO), 3701 N. Fairfax Dr., Arlington, VA 22203-1714

ZIP Code

22203-1714

Solicitation Number

BAA 01-20

Response Due

January 24, 2001

Point of Contact

Dr. William Phillips, DARPA/TTO; FAX: (703) 522-7161

Description

MISSION SPECIFIC PROCESSING, SOL BAA 01-20, DUE: 01/24/01; POC: DR. WILLIAM PHILLIPS, DARPA/TTO; FAX: (703) 522-7161. PROGRAM DESCRIPTION: The Defense Advanced Research Projects Agency (DARPA) is soliciting proposals for research on various aspects of highly optimized, fixed function, Digital Signal Processing (DSP) Application Specific Integrated Circuit (ASIC) development under the Mission Specific Processing (MSP) program. This BAA solicits research to explore, identify, and refine custom design techniques and mission level optimizations that offer increased ASIC performance for the most highly constrained processing systems in the DoD. The specific missions of interest have constraints on size, weight, and power that preclude the use of general purpose programmable or re-configurable processing solutions. DARPA is interested in designs that benefit specific military applications where a significant improvement in mission utility can be achieved through highly customized ASICs. The ASIC designs are expected to include both specialized programmable and fixed function components.Several future miniature and space based systems require processing approaches that achieve a sustained processing throughput of greater than 200 billions of operations per second per watt (GOPS/W). Example missions include wideband multi-channel adaptive radar processing, image and signal processing for micro unmanned air vehicles (MUAVs), wideband communications, space based sensor processing, and miniaturized missile seekers. For these critical missions, increased ASIC customization can enhance performance as well as enable new capability. There exists a scattered technology base in the research and commercial communities where by custom techniques are utilized to increase performance over traditionTheseSeveral custom techniques may achieve performance increases relative to traditional standard cell ASICs through transistor and cell level optimizations. Example techniques include the use of enhanced or custom cell libraries, macro cells, macro generators for key DSP kernels, custom data path layout tools, dynamic logic,, custom programmable devices, and other custom design approaches. The most beneficial customization techniques will be adopted to achieve a significant increase in performance relative to traditional standard cell ASIC design approaches. It should be noted that the intention of MSP is not to develop new computer aided design (CAD) tools, but to work within the framework of the existing commercial CAD infrastructure, augmenting these CAD tools only on an as needed basis. The design flow for ASIC development should include commercial hardware descriptive language (HDL) synthesis tools and any customized cell libraries or tools should be compatible with commercial synthesis tools. The goal is to explore the design space between standard cell ASIC approaches and full custom design approaches, identifying those methods of customization that offer the maximum performance benefit as measured by performance/watt and/or peak throughput with the minimum impact on design time. The custom design methods with the smallest impact on design time and cost will be used to design custom components for critical DoD systems. Using the smallest feature size process available is not the primary goal of the program. It is more important to develop scalable techniques that can be reused in future process technologies. The demonstration of MSP technology is to be accomplished through the design of full scale ASICs and the integration of the completed ASICs into a breadboard test system. The test system should be representative of a real application in that real or synthetic data is processed at the rate required by the selected application. The demonstration should be functionally complete, address system level issues, and quantify the increased performance relative to traditional ASIC designs, field programmable gate arrays (FPGAs), and commercial off the shelf (COTS) processors. The technology and systems developed should be scalable and any new CAD like software should be applicable to future designs. PROGRAM SCOPE: Proposed research should investigate innovative approaches and techniques that lead to or enable significant advances in DoD mission capability through customized ASIC design approaches and novel architectures. Proposals are not limited to the specific strategies listed above and alternative visions will be considered. However, proposals should be for research that substantially contributes towards the stated goals. Research should result in prototype systems demonstrating integrated concepts and approaches. Proposals may involve other research groups or industrial cooperation and cost sharing. Mission Specific Processing is a new four year program beginning in FY2001. The program is divided into two phases where each phase of the program lasts for 2 years. Phase 1 efforts should explore the design space between traditional standard cell ASIC design and full custom design to identify the most beneficial methods of increasing performance in signal processing ASICs. The selected methods of customization should be matured to the point that full scale ASIC development can take place in Phase 2. Also included in the Phase 1 investigation is the development of novel high level ASIC architectures that benefit specific missions. An important element of the Phase 1 work will be detailed documentation of the Phase 1 activities such as benchmarking, cell library design, and macro compiler design. Also included in the documentation is any other material necessary to ensure the longevity of the technology and to provide a successful transition to Phase 2 of the program. The Phase 1 investigations should conclude with detailed simulations or the fabrication of test chips demonstrating increases in performance based on the selected methods. Phase 2 of the program consists of full scale ASIC development using the architectures and techniques selected in Phase 1. The Phase 2 development and demonstrations of the processing components should be included as option years. Mission specific technology development under Phase 2 of the MSP program is expected to be covered under the International Traffic in Arms Regulations (ITAR). The total program funding is $27.7M with $5.7M in FY2001, $9.0M in FY02, $9.5M in FY03, and $3.5M in FY04. Multiple awards are expected. GENERAL INFORMATION: The Defense Advanced Research Projects Agency/Information Technology Office (DARPA/TTO) requires completion of a Broad Agency Announcement (BAA) Cover Sheet Submission for each Proposal, by accessing the URL below: http://www.dyncorp-is.com/BAA/index.asp?BAAid=01-20. After finalizing the BAA Cover Sheet Submission, the proposer must submit the BAA Confirmation Sheet that will automatically appear on the web page. Each proposer is responsible for printing the BAA Confirmation Sheet and submitting it attached to the "original" and each designated number of copies. The Confirmation Sheet should be the first page of your Proposal. Failure to comply with these submission procedures may result in the submission not being evaluated. Detailed information and instructions are outlined within the Proposer Information Pamphlet (PIP). PROPOSAL FORMAT: Proposers must submit an original and 4 copies of the full proposal and 4 electronic copies (i.e., 4 separate disks) of the full proposal (in Microsoft Word '97 for IBM-compatible, PDF, Postscript, or ASCII format on one 3.5-inch floppy disk or one 100 MB Iomega Zip disk). Each disk must be clearly labeled with BAA 01-20, proposer organization, proposal title (short title recommended) and Copy ___ of 4). The full proposal (original and designated number of hard and electronic copies) must be submitted in time to reach DARPA by 4:00 PM (ET) Wednesday, January 24, 2001, in order to be considered. Proposers must obtain the BAA 01-20 Proposer Information Pamphlet (PIP), which provides further information on the areas of interest, submission, evaluation, funding processes, and full proposal formats. This pamphlet may be obtained by fax, electronic mail, mail request to the administrative contact address given below, or at URL address http://www.darpa.mil/tto/Solicitations.html. Proposals not meeting the format described in the pamphlet may not be reviewed. This Commerce Business Daily (CBD) notice, in conjunction with the BAA 01-20 PIP and all references, constitutes the total BAA. No additional information is available, nor will a formal RFP or other solicitation regarding this announcement be issued. Requests for same will be disregarded. The Government reserves the right to select for award all, some, or none of the proposals received. All responsible sources capable of satisfying the Government's needs may submit a proposal that shall be considered by DARPA. Historically Black Colleges and Universities (HBCUs) and Minority Institutions (MIs) are encouraged to submit proposals and join others in submitting proposals. However, no portion of this BAA will be set aside for HBCU and MI participation due to the impracticality of reserving discrete or severable areas of this research for exclusive competition among these entities. Evaluation of proposals will be accomplished through a scientific review of each proposal using the following criteria, which are listed in descending order of relative importance: (1) Overall Scientific and Technical Merit: The overall scientific and technical merit must be clearly identifiable. The technical concept should be clearly defined and developed. Emphasis should be placed on the technical value of the development and experimentation approach. (2) Innovative Technical Solution to the Problem: Proposed efforts should apply new or existing technology in a new way such as is advantageous to the objectives. The plan on how offeror intends to get developed technology and information to the user community should be considered. (3) Potential Contribution and Relevance to DARPA Mission: The offeror must clearly address how the proposed effort will meet the goals of the undertaking. The relevance is further indicated by the offeror's understanding of the operating environment of the capability to be developed. (4) Offeror's Capabilities and Related Experience: The qualifications, capabilities, and demonstrated achievements of the proposed principals and other key personnel for the primary and subcontractor organizations must be clearly shown. (5) Plans and Capability to Accomplish Technology Transition: The offeror should provide a clear explanation of how the technologies to be developed will be transitioned to capabilities for military forces. Technology transition should be a major consideration in the design of experiments, particularly considering the potential for involving potential transition organizations in the experimentation process. (6) Cost Realism: The overall estimated cost to accomplish the effort should be clearly shown as well as the substantiation of the costs for the technical complexity described. Evaluation will consider the value to Government of the research and the extent to which the proposed management plan will effectively allocate resources to achieve the capabilities proposed. All administrative correspondence and questions on this solicitation, including requests for information on how to submit a proposal to this BAA, must be received at one of the administrative addresses below by 4:00 PM (ET) January 17, 2001, e-mail or fax is preferred. DARPA intends to use electronic mail and fax for some of the correspondence regarding BAA 01-20. Proposals MUST NOT be submitted by fax or e-mail; any so sent will be disregarded. The administrative addresses for this BAA are: Fax: 703-522-7161 Addressed to: DARPA/TTO, BAA 01-20; Electronic Mail: baa01-20@darpa.mil; Electronic File Retrieval: http://www.darpa.mil/tto/Solicitations.html; Mail to: DARPA/TTO, ATTN: BAA 01-20, 3701 N. Fairfax Drive, Arlington, VA 22203-1714.

Record

Loren Data Corp. 20001212/ASOL004.HTM (W-343 SN5084G7)