A -- BIT STREAM GENERATOR

Notice Date

March 21, 2001

Contracting Office

DOC; Mountain Administrative Support Center; Acquisition Management Division; 325 Broadway MC3; Boulder, CO 80303-3328

ZIP Code

80303-3328

Solicitation Number

NB814000104045JW

Response Due

April 19, 2001

Point of Contact

Jacqueline Wright (303) 497-5282, FAX (303) 497-3163

E-Mail Address

NOAA; MASC Acquisitions Management (Jacqueline.S.Wright@noaa.gov)

Description

The National Institute of Standards and Technology (NIST) has a requirement for a Bit Stream Generator. In order to further the aims of the ac Josephson voltage standard, we require a custom high-speed bit stream generator. This system shall supply a user-defined series of pulses that shall be applied to our Josephson array to produce the desired ac waveform. This bit stream generator shall be an integral part of the future ac Josephson voltage standard system. The intent of this requirement is to generate a design and a single prototype that will serve as a model for all future systems for use with the ac Josephson voltage standard system. The system shall: 1) serialize digital data in memory and stream it out at a rate of 1 bit every 100 picoseconds, cycle this data with no delay between repetitions until it receives a command to use different data and be in a standard 19 inch rack mountable unit; 2) have an output data rate of 10 Giga bits per second (Gbps). This rate shall be derived from a standard 10 MHz or 155 MHz reference input clock. The output bit stream shall be programmed into the unit from an external computer using standard 100 Mbit/second technology; 3) be able to store up to 1 Giga bit of data and shall be able to switch between up to 8 different codes that may fill up the entire memory of the system; and 4) the amplitude of the output waveform shall be adjustable from a minimum range of 0.5V to 2V in with a maximum increment of 0.01V. The output bit stream DC offset level shall be adjustable with a minimum range -2.35V to +1.5V with a maximum increment of 0.01V. The relative phase delay of the output bit stream shall be adjustable from at least minus 1 nanosecond to plus 1 nanosecond in maximum increments of 1picosecond. The stability of the relative phase delay shall be 1 picosecond rms per hour, and 1 picosecond rms per degree Celsius. The internal features shall meet or exceed ITU-958 specifications for timing jitter. There shall be three rear-panel inputs to this unit: 1. 120 V ac power of less than 10 amperes 2. A RJ45 ethernet connection 3. A 10 MHz synchronization BNC jack. The internal power to the unit shall be from a linear power supply, not a switching power supply for noise reasons. The front panel shall have the following input/outputs with SMA connectors: 1. The 10 Gbps bit stream output (DATA). 2. A complementary bit stream output (complementary DATA) 3. A 155 MHz clock input 4. A 155 MHz clock output 5. A Frame sync output indicating the start of a new code 6. Three Scope sync outputs 7. A Master/Slave input for this unit to have its timing controlled from another similar unit 8. Eight Master/Slave trigger outputs to control the timing of similar units. 9. Eight Auxiliary Input/Outputs connected to the internal FPGA for future use There shall be front panel indicator LEDs on the unit to display: 1. Power to the unit 2. Ethernet activity: receive and transmit 3. Output activity (code running) 4. Clock lock for each internal synchronization stage 5. Three spare LEDs for future use The system shall be able to synchronize from either the 10 MHz reference or the 155 MHz reference. There shall be a user interface to adjust the following: 1. Output amplitude 2. Output DC offset level 3. Phase delay 4. Output Enable/Disable 5. Load code #n 6. Run code #n 7. Report current code # 8. Get status 9. Manual code entry for short codes. The unit shall receive all these adjustments via the Ethernet port and firmware shall be provided to facilitate the software implementation. When the 10 Gbps output of the system is disabled, the unit shall have at least 50 Ohms output impedance. There shall be a serial output to connect to a standard serial device that may be used for debugging purposes. The graphical user interface shall be written in a standard scripting language that is portable across many host platforms. The interface shall allow a user to read in a code to the unit, start it, adjust the various levels and phase delay, turn off the output, and switch to another code. All designs, schematics, verilog code, and other source code shall be provided to NIST. There shall be three reviews of the design with NIST personnel before the design is to be prototyped. Ranking factors are as follows: 1) Technical merit of proposal (meeting specifications and using proven technologies ) 25 % 2) Use of commercially available components 10 % 3) References as a vendor with proven high speed FPGA experience 25 % 4) Economical design for larger scale manufacture 15 % 5) Cost of design/prototype phase 25 % NIST personnel shall have final approval before the prototype is built. Interested sources must submit a written qualification statement with literature, by March 28, 2001, and must contain sufficient information to clearly establish the ability to provide the required prototype system. Responses must reference Synopsis No. NB814000104045JW. This announcement/solicitation is being issued under the Simplified Acquisition Procedures, FAR Part 13 (NTE $100,000.00). All rights in any type of data, recorded information, schematics, layouts or software created under this agreement shall be allocated in accordance with the Federal Acquisition Regulations Title 48 CFR Part 52.227-17 Rights in Data -- Special Works. There is no bid package available, as all the requirements are listed above. The bids must be received by close of business April 19, 2001. The award decision will be based upon the best value to the Government, with technical merit, past performance and availability being significantly more important than price. A technical panel will evaluate the responses. Terms and Conditions and agency level protest procedures are referenced at http://netsite.esa.doc.gov.oam. JACQUELINE WRIGHT Purchasing Agent

Record

Loren Data Corp. 20010323/ASOL015.HTM (D-080 SN50G9F6)